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https://github.com/openhwgroup/cvw
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Improved LSU formating.
This commit is contained in:
Ross Thompson
parent
ad22a9ea02
commit
318ceba34d
@ -7,6 +7,8 @@
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//
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// Purpose: RISC-V Arithmetic/Logic Unit
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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@ -6,8 +6,10 @@
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// Modified: 11 January 2023
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//
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// Purpose: Load/Store Unit
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// Top level of the memory-stage core logic
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// Contains data cache, DTLB, subword read/write datapath, interface to external bus
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// HPTW, DMMU, data cache, interface to external bus
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// Atomic, Endian swap, and subword read/write logic
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//
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// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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@ -27,97 +29,120 @@
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// and limitations under the License.
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
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// committed means the memory operation in flight cannot be interrupted.
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// chap 5 handling faults to memory by delaying writes to memory stage.
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// chap 6 combing bus with dtim
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// chap 9 complete lsu.
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`include "wally-config.vh"
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM,
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation.
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// connected to cpu (controls)
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicM,
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input logic FlushDCacheM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic DCacheMiss,
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output logic DCacheAccess,
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE,
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(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
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(* mark_debug = "true" *)input logic [`XLEN-1:0] WriteDataM,
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output logic [`LLEN-1:0] ReadDataW,
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input logic [`XLEN-1:0] IEUAdrE, // Execution stage memory address
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(* mark_debug = "true" *) output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address
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(* mark_debug = "true" *) input logic [`XLEN-1:0] WriteDataM, // Write data from IEU
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output logic [`LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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// cpu privilege
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input logic [1:0] PrivilegeModeW,
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input logic BigEndianM,
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input logic sfencevmaM,
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence
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// fpu
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input logic [`FLEN-1:0] FWriteDataM,
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input logic FpLoadStoreM,
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input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM, HPTWInstrAccessFaultM,
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output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic HPTWInstrAccessFaultM, // HPTW generated access fault during instruction fetch
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM,
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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// connect to ahb
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA,
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(* mark_debug = "true" *) input logic LSUHREADY,
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(* mark_debug = "true" *) output logic LSUHWRITE,
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(* mark_debug = "true" *) output logic [2:0] LSUHSIZE,
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(* mark_debug = "true" *) output logic [2:0] LSUHBURST,
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(* mark_debug = "true" *) output logic [1:0] LSUHTRANS,
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(* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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(* mark_debug = "true" *) input logic LSUHREADY, // Bus ready from LSU to EBU
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(* mark_debug = "true" *) output logic LSUHWRITE, // Bus write operation from LSU to EBU
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(* mark_debug = "true" *) output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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(* mark_debug = "true" *) output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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(* mark_debug = "true" *) output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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(* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [`XLEN-1:0] PCF,
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input logic ITLBMissF,
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input logic InstrDAPageFaultF,
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output logic [`XLEN-1:0] PTE,
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output logic [1:0] PageType,
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output logic ITLBWriteF, SelHPTW,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
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input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic [`XLEN-1:0] PCF, // Fetch PC
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits
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output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit
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);
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logic [`XLEN+1:0] IEUAdrExtM;
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logic [`XLEN+1:0] IEUAdrExtE;
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logic [`PA_BITS-1:0] PAdrM;
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logic DTLBMissM;
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logic DTLBWriteM;
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logic [1:0] PreLSURWM, LSURWM;
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logic [2:0] LSUFunct3M;
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logic [6:0] LSUFunct7M;
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logic [1:0] LSUAtomicM;
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(* mark_debug = "true" *) logic [`XLEN+1:0] IHAdrM;
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logic GatedStallW;
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logic DCacheStallW;
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logic CacheableM;
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logic BusStall;
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logic HPTWStall;
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logic IgnoreRequestTLB;
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logic BusCommittedM, DCacheCommittedM;
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logic DataDAPageFaultM;
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logic [`XLEN-1:0] IHWriteDataM, IMAWriteDataM;
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logic [`LLEN-1:0] IMAFWriteDataM;
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logic [`LLEN-1:0] ReadDataM;
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logic [(`LLEN-1)/8:0] ByteMaskM;
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logic SelDTIM;
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logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM;
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logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [`XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [`PA_BITS-1:0] PAdrM; // Physical memory address
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(* mark_debug = "true" *) logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address
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logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal
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logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC
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logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size
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logic [6:0] LSUFunct7M; // AMO function gated by HPTW
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logic [1:0] LSUAtomicM; // AMO signal gated by HPTW
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logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
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logic DCacheStallW; // D$ busy with multicycle operation
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logic BusStall; // Bus interface busy with multicycle operation
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logic HPTWStall; // HPTW busy with multicycle operation
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logic CacheableM; // PMA indicates memory address is cacheable
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logic BusCommittedM; // Bus memory operation in flight, delay interrupts
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logic DCacheCommittedM; // D$ memory operation started, delay interrupts
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logic [`LLEN-1:0] DTIMReadDataWordM; // DTIM read data
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logic [`LLEN-1:0] DCacheReadDataWordM; // D$ read data
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logic [`LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
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logic [`LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data
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logic [`LLEN-1:0] ReadDataWordM; // Read data before subword selection
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logic [`LLEN-1:0] ReadDataM; // Final read data
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logic [`XLEN-1:0] IHWriteDataM; // IEU or HPTW write data
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logic [`XLEN-1:0] IMAWriteDataM; // IEU, HPTW, or AMO write data
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logic [`LLEN-1:0] IMAFWriteDataM; // IEU, HPTW, AMO, or FPU write data
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logic [`LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data
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logic [`LLEN-1:0] LSUWriteDataM; // Final write data
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logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE to DTLB
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logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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logic IgnoreRequest; // On FlushM, ignore TLB miss
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logic SelDTIM; // Select DTIM rather than bus or D$
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Pipeline for IEUAdr E to M
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// Zero-extend address to 34 bits for XLEN=32
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/////////////////////////////////////////////////////////////////////////////////////////////
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign IEUAdrExtE = {2'b00, IEUAdrE};
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assign LSUStallM = DCacheStallW | HPTWStall | BusStall;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// HPTW (only needed if VM supported)
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@ -129,81 +154,72 @@ module lsu (
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.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
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.FlushW, .DCacheStallW, .SATP_REGW, .PCF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
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.ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
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.ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
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.WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
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.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
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.IHAdrM, .HPTWStall, .SelHPTW,
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.IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultM);
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end else begin
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assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
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end else begin // No HPTW, so signals are not multiplexed
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assign PreLSURWM = MemRWM;
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assign IHAdrM = IEUAdrExtM;
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assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
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assign LSUFunct3M = Funct3M;
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assign LSUFunct7M = Funct7M;
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assign LSUAtomicM = AtomicM;
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assign IHWriteDataM = WriteDataM;
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assign LoadAccessFaultM = LSULoadAccessFaultM;
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assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;
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assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
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assign HPTWInstrAccessFaultM = '0;
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end
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// CommittedM tells the CPU's privilege unit the current instruction
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// in the memory stage is a memory operaton and that memory operation is either completed
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// or is partially executed. Partially completed memory operations need to prevent an interrupts.
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// There is not a clean way to restore back to a partial executed instruction. CommiteedM will
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// delay the interrupt until the LSU is in a clean state.
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// CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation.
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// CommittedM is 1 after the first cycle and until the last cycle. Partially completed memory
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// operations delay interrupts until the next instruction by suppressing pending interrupts in
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// the trap module.
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assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
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assign GatedStallW = StallW & ~SelHPTW;
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assign LSUStallM = DCacheStallW | HPTWStall | BusStall;
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// MMU and Misalignment fault logic required if privileged unit exists
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/////////////////////////////////////////////////////////////////////////////////////////////
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// MMU and misalignment fault logic required if privileged unit exists
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`ZICSR_SUPPORTED == 1) begin : dmmu
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logic DisableTranslation;
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logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation,
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.VAdr(IHAdrM),
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.Size(LSUFunct3M[1:0]),
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.PTE,
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.PageTypeWriteVal(PageType),
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.TLBWrite(DTLBWriteM),
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.TLBFlush(sfencevmaM),
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.PhysicalAddress(PAdrM),
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.TLBMiss(DTLBMissM),
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.Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
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.InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM), .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM),
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.InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
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.PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
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.PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
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.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
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.InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM),
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.StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM,
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.StoreAmoPageFaultM,
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw.
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.DAPageFault(DataDAPageFaultM),
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// *** should use LSURWM as this is includes the lr/sc squash. However this introduces a combo loop
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// from squash, depends on PAdrM, depends on TLBHit, depends on these *AccessM inputs.
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.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
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.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin
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// Determine which region of physical memory (if any) is being accessed
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// conditionally move adredecs to here and ifu.
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// the lsu will output LSUHSel to EBU (need the same for ifu).
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// The ebu will have a mux to select between LSUHSel, IFUHSel
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// mux for HWSTRB
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// adrdecs out of uncore.
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end else begin // No MMU, so no PMA/page faults and no address translation
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assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
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assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
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assign PAdrM = IHAdrM[`PA_BITS-1:0];
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assign CacheableM = '1;
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assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no pma then select dtim if there is a DTIM. If there is
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assign CacheableM = 1'b1;
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assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no PMA then select dtim if there is a DTIM. If there is
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// a bus then this is always 0. Cannot have both without PMA.
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Memory System
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// Either Data Cache or Data Tightly Integrated Memory or just bus interface
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// Memory System (options)
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// 1. DTIM
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// 2. DTIM and bus
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// 3. Bus
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// 4. Cache and bus
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/////////////////////////////////////////////////////////////////////////////////////////////
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logic [`LLEN-1:0] LSUWriteDataM, LittleEndianWriteDataM;
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logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM;
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logic [`LLEN-1:0] ReadDataWordMuxM, DTIMReadDataWordM, DCacheReadDataWordM;
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logic IgnoreRequest;
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// Pause IEU memory request if TLB miss. After TLB fill, replay request.
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// Discard memory request on pipeline flush
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assign IgnoreRequest = IgnoreRequestTLB | FlushW;
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||||
|
||||
if (`DTIM_SUPPORTED) begin : dtim
|
||||
@ -211,7 +227,7 @@ module lsu (
|
||||
logic [1:0] DTIMMemRWM;
|
||||
|
||||
// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
|
||||
assign DTIMAdr = MemRWM[0] ? IEUAdrExtM[`PA_BITS-1:0] : IEUAdrExtE[`PA_BITS-1:0]; // zero extend or contract to PA_BITS
|
||||
mux2 #(`PA_BITS) DTIMAdrMux(IEUAdrExtE[`PA_BITS-1:0], IEUAdrExtM[`PA_BITS-1:0], MemRWM[0], DTIMAdr);
|
||||
assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
|
||||
// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
|
||||
// **** create config to support DTIM with floating point.
|
||||
@ -221,12 +237,12 @@ module lsu (
|
||||
end else begin
|
||||
end
|
||||
if (`BUS) begin : bus
|
||||
localparam integer LLENWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`LLEN : 1;
|
||||
localparam integer LLENLOGBWPL = `DCACHE ? $clog2(LLENWORDSPERLINE) : 1;
|
||||
localparam integer BEATSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1;
|
||||
localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(BEATSPERLINE) : 1;
|
||||
localparam integer LLENWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`LLEN : 1; // Number of LLEN words in cacheline
|
||||
localparam integer LLENLOGBWPL = `DCACHE ? $clog2(LLENWORDSPERLINE) : 1; // Log2 of ^
|
||||
localparam integer BEATSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1; // Number of ABHW words (beats) in cacheline
|
||||
localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(BEATSPERLINE) : 1; // Log2 of ^
|
||||
if(`DCACHE) begin : dcache
|
||||
localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
|
||||
localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; // Number of bytes in cacheline
|
||||
logic [LINELEN-1:0] FetchBuffer;
|
||||
logic [`PA_BITS-1:0] DCacheBusAdr;
|
||||
logic [AHBWLOGBWPL-1:0] BeatCount;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user