Signal name changes.

src/hazard/hazard.sv

@@ -30,7 +30,7 @@
 
 module hazard (
   // Detect hazards
-  input logic  BPPredWrongE, CSRWriteFenceM, RetM, TrapM,   
+  input logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
   input logic  LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
   input logic  LSUStallM, IFUStallF,
   input logic  FCvtIntStallD, FPUStallD,
@@ -65,8 +65,8 @@ module hazard (
   // Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents
   // Branch misprediction is found in the Execute stage and must flush the next two instructions.
   //   However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete
-  assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE;
+  assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPWrongE;
-  assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE));
+  assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE));
   assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
   assign FlushWCause = TrapM;
 

src/ifu/bpred/bpred.sv

@@ -62,7 +62,7 @@ module bpred (
   output logic             JumpOrTakenBranchM,        // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
 
   // Report branch prediction status
-  output logic             BPPredWrongE,              // Prediction is wrong
+  output logic             BPWrongE,              // Prediction is wrong
   output logic             BPPredWrongM,              // Prediction is wrong
   output logic             BPDirPredWrongM,           // Prediction direction is wrong
   output logic             BTBPredPCWrongM,           // Prediction target wrong
@@ -73,7 +73,7 @@ module bpred (
   logic [1:0] 		   BPDirPredF;
 
   logic [`XLEN-1:0] 	   BTAF, RASPCF;
-  logic 		   PredictionPCWrongE;
+  logic 		   BPPCWrongE;
   logic 		   AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
   logic 		   BPDirPredWrongE;
   
@@ -157,7 +157,6 @@ module bpred (
           .InstrClassM({CallM, ReturnM, JumpM, BranchM}),
           .InstrClassW({CallW, ReturnW, JumpW, BranchW}));
 
-
   icpred icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
 		.PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
 		.CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF,
@@ -174,10 +173,10 @@ module bpred (
   // this will result in PCD not being equal to the fall through address PCLinkE (PCE+4).
   // The next instruction is always valid as no other flush would occur at the same time as the branch and not
   // also flush the branch.  This will change in a superscaler cpu. 
-  assign PredictionPCWrongE = PCCorrectE != PCD;
+  assign BPPCWrongE = PCCorrectE != PCD;
   // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
-  assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
+  assign BPWrongE = BPPCWrongE & InstrValidE & InstrValidD;
-  flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
+  flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPPredWrongM);
   
   // Output the predicted PC or corrected PC on miss-predict.
   assign BPPCSrcF = (BPBranchF & BPDirPredF[1]) | BPJumpF;
@@ -185,7 +184,7 @@ module bpred (
   // Selects the BP or PC+2/4.
   mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PCNext0F);
   // If the prediction is wrong select the correct address.
-  mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);  
+  mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPWrongE, PCNext1F);  
   // Correct branch/jump target.
   mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
   

src/ifu/ifu.sv

@@ -54,7 +54,7 @@ module ifu (
   input  logic [`XLEN-1:0] 	IEUAdrE,                                  // The branch/jump target address
   input  logic [`XLEN-1:0] 	IEUAdrM,                                  // The branch/jump target address
   output logic [`XLEN-1:0] 	PCE,                                      // Execution stage instruction address
-  output logic 				BPPredWrongE,                             // Prediction is wrong
+  output logic 				BPWrongE,                             // Prediction is wrong
   output logic 				BPPredWrongM,                             // Prediction is wrong
   // Mem
   output logic              CommittedF,                               // I$ or bus memory operation started, delay interrupts
@@ -331,12 +331,12 @@ module ifu (
                 .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, 
                 .BranchD, .BranchE, .JumpD, .JumpE,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
-                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
+                .PCD, .PCLinkE, .InstrClassM, .BPWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
                 .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
 
   end else begin : bpred
     mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F));    
-    assign BPPredWrongE = PCSrcE;
+    assign BPWrongE = PCSrcE;
     assign {InstrClassM, BPDirPredWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM} = '0;
     assign NextValidPCE = PCE;
   end      

src/wally/wallypipelinedcore.sv

@@ -140,7 +140,7 @@ module wallypipelinedcore (
   logic                          LSUHWRITE;
   logic                          LSUHREADY;
   
-  logic                          BPPredWrongE, BPPredWrongM;
+  logic                          BPWrongE, BPPredWrongM;
   logic                          BPDirPredWrongM;
   logic                          BTBPredPCWrongM;
   logic                          RASPredPCWrongM;
@@ -173,7 +173,7 @@ module wallypipelinedcore (
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
     .ICacheAccess, .ICacheMiss,
     // Execute
-    .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPPredWrongE,  .BPPredWrongM, 
+    .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE,  .BPPredWrongM, 
     // Mem
     .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
     .InstrD, .InstrM, .PCM, .InstrClassM, .BPDirPredWrongM, .JumpOrTakenBranchM,
@@ -268,7 +268,7 @@ module wallypipelinedcore (
 
   // global stall and flush control  
   hazard  hzu(
-    .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
+    .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
     .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
     .LSUStallM, .IFUStallF,
     .FCvtIntStallD, .FPUStallD,