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Improved address bus names and usages in the walker, dcache, and tlbs.

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Merge branch 'walkerEnhance' into main
This commit is contained in:
Ross Thompson 2021-07-21 14:55:09 -05:00
commit 313bc5255c
10 changed files with 100 additions and 95 deletions
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1
wally-pipelined/regression/wave.do
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@ -419,7 +419,6 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/Address
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR

8
wally-pipelined/src/cache/dcache.sv vendored
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@ -38,8 +38,9 @@ module dcache
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
input logic [6:0] Funct7M, input logic [6:0] Funct7M,
input logic [1:0] AtomicM, input logic [1:0] AtomicM,
input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] MemPAdrM, // physical address input logic [`PA_BITS-1:0] MemPAdrM, // physical address
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
input logic [`XLEN-1:0] WriteDataM, input logic [`XLEN-1:0] WriteDataM,
output logic [`XLEN-1:0] ReadDataW, output logic [`XLEN-1:0] ReadDataW,
@ -200,10 +201,11 @@ module dcache
// data path // data path
mux2 #(INDEXLEN) mux3 #(INDEXLEN)
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.s(SelAdrM), .d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.s({DTLBWriteM, SelAdrM}),
.y(SRAMAdr)); .y(SRAMAdr));

7
wally-pipelined/src/ifu/ifu.sv
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@ -101,7 +101,8 @@ module ifu (
logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; logic PMPInstrAccessFaultF, PMAInstrAccessFaultF;
logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
logic [`XLEN+1:0] PCFExt;
generate generate
if (`XLEN==32) begin if (`XLEN==32) begin
@ -113,8 +114,10 @@ module ifu (
end end
endgenerate endgenerate
assign PCFExt = {2'b00, PCF};
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1)) mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
immu(.Address(PCF), immu(.PAdr(PCFExt[`PA_BITS-1:0]),
.VAdr(PCF),
.Size(2'b10), .Size(2'b10),
.PTE(PTE), .PTE(PTE),
.PageTypeWriteVal(PageType), .PageTypeWriteVal(PageType),

68
wally-pipelined/src/lsu/lsu.sv
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@ -125,16 +125,14 @@ module lsu
logic HPTWStall; logic HPTWStall;
logic [`XLEN-1:0] HPTWPAdrE; logic [`XLEN-1:0] HPTWPAdrE;
// logic [`XLEN-1:0] HPTWPAdrM; // logic [`XLEN-1:0] HPTWPAdrM;
logic [`XLEN-1:0] TranslationVAdr;
logic [`PA_BITS-1:0] TranslationPAdr; logic [`PA_BITS-1:0] TranslationPAdr;
logic UseTranslationVAdr;
logic HPTWRead; logic HPTWRead;
logic [1:0] MemRWMtoDCache; logic [1:0] MemRWMtoDCache;
logic [1:0] MemRWMtoLRSC; logic [1:0] MemRWMtoLRSC;
logic [2:0] Funct3MtoDCache; logic [2:0] Funct3MtoDCache;
logic [1:0] AtomicMtoDCache; logic [1:0] AtomicMtoDCache;
logic [`XLEN-1:0] MemAdrMtoDCache; logic [`PA_BITS-1:0] MemPAdrMtoDCache;
logic [`XLEN-1:0] MemAdrEtoDCache; logic [11:0] MemAdrEtoDCache;
logic [`XLEN-1:0] ReadDataWfromDCache; logic [`XLEN-1:0] ReadDataWfromDCache;
logic StallWtoDCache; logic StallWtoDCache;
logic MemReadM; logic MemReadM;
@ -154,35 +152,27 @@ module lsu
hptw hptw( hptw hptw(
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.SATP_REGW(SATP_REGW), .SATP_REGW(SATP_REGW),
.PCF(PCF), .PCF(PCF),
.MemAdrM(MemAdrM), .MemAdrM(MemAdrM),
.ITLBMissF(ITLBMissF), .ITLBMissF(ITLBMissF),
.DTLBMissM(DTLBMissM), .DTLBMissM(DTLBMissM),
.MemRWM(MemRWM), .MemRWM(MemRWM),
.PTE(PTE), .PTE(PTE),
.PageType, .PageType,
.ITLBWriteF(ITLBWriteF), .ITLBWriteF(ITLBWriteF),
.DTLBWriteM(DTLBWriteM), .DTLBWriteM(DTLBWriteM),
.HPTWReadPTE(HPTWReadPTE), .HPTWReadPTE(HPTWReadPTE),
.HPTWStall(HPTWStall), .HPTWStall(HPTWStall),
.TranslationVAdr, .TranslationPAdr,
.TranslationPAdr, .HPTWRead(HPTWRead),
.UseTranslationVAdr, .SelPTW(SelPTW),
.HPTWRead(HPTWRead), .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
.SelPTW(SelPTW), .WalkerLoadPageFaultM(WalkerLoadPageFaultM),
.WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerStorePageFaultM(WalkerStorePageFaultM));
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
.WalkerStorePageFaultM(WalkerStorePageFaultM));
logic [`XLEN-1:0] TranslationPAdrXLEN;
generate // *** needs fixing about truncation dh 7/17/21
if (`XLEN == 32) assign TranslationPAdrXLEN = TranslationPAdr[31:0];
else assign TranslationPAdrXLEN = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
endgenerate
mux2 #(`XLEN) HPTWPAdrMux(TranslationPAdrXLEN, TranslationVAdr, UseTranslationVAdr, HPTWPAdrE); // *** misleading to call it PAdr, bad because some bits have been truncated
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM; assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
@ -192,7 +182,7 @@ module lsu
// HPTW connection // HPTW connection
.SelPTW(SelPTW), .SelPTW(SelPTW),
.HPTWRead(HPTWRead), .HPTWRead(HPTWRead),
.HPTWPAdrE(HPTWPAdrE), .TranslationPAdrE(TranslationPAdr),
.HPTWStall(HPTWStall), .HPTWStall(HPTWStall),
// CPU connection // CPU connection
.MemRWM(MemRWM), .MemRWM(MemRWM),
@ -211,7 +201,7 @@ module lsu
.MemRWMtoLRSC(MemRWMtoLRSC), .MemRWMtoLRSC(MemRWMtoLRSC),
.Funct3MtoDCache(Funct3MtoDCache), .Funct3MtoDCache(Funct3MtoDCache),
.AtomicMtoDCache(AtomicMtoDCache), .AtomicMtoDCache(AtomicMtoDCache),
.MemAdrMtoDCache(MemAdrMtoDCache), .MemPAdrMtoDCache(MemPAdrMtoDCache),
.MemAdrEtoDCache(MemAdrEtoDCache), .MemAdrEtoDCache(MemAdrEtoDCache),
.StallWtoDCache(StallWtoDCache), .StallWtoDCache(StallWtoDCache),
.DataMisalignedMfromDCache(DataMisalignedMfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache),
@ -224,7 +214,8 @@ module lsu
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.Address(MemAdrMtoDCache), dmmu(.PAdr(MemPAdrMtoDCache),
.VAdr(MemAdrM),
.Size(Funct3MtoDCache[1:0]), .Size(Funct3MtoDCache[1:0]),
.PTE(PTE), .PTE(PTE),
.PageTypeWriteVal(PageType), .PageTypeWriteVal(PageType),
@ -269,9 +260,9 @@ module lsu
always_comb always_comb
case(Funct3MtoDCache[1:0]) case(Funct3MtoDCache[1:0])
2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu 2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu
2'b01: DataMisalignedMfromDCache = MemAdrMtoDCache[0]; // lh, sh, lhu 2'b01: DataMisalignedMfromDCache = MemPAdrMtoDCache[0]; // lh, sh, lhu
2'b10: DataMisalignedMfromDCache = MemAdrMtoDCache[1] | MemAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu 2'b10: DataMisalignedMfromDCache = MemPAdrMtoDCache[1] | MemPAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu
2'b11: DataMisalignedMfromDCache = |MemAdrMtoDCache[2:0]; // ld, sd, fld, fsd 2'b11: DataMisalignedMfromDCache = |MemPAdrMtoDCache[2:0]; // ld, sd, fld, fsd
endcase endcase
// Squash unaligned data accesses and failed store conditionals // Squash unaligned data accesses and failed store conditionals
@ -312,6 +303,7 @@ module lsu
.AtomicM(AtomicMtoDCache), .AtomicM(AtomicMtoDCache),
.MemAdrE(MemAdrEtoDCache), .MemAdrE(MemAdrEtoDCache),
.MemPAdrM(MemPAdrM), .MemPAdrM(MemPAdrM),
.VAdr(MemAdrM[11:0]),
.WriteDataM(WriteDataM), .WriteDataM(WriteDataM),
.ReadDataW(ReadDataWfromDCache), .ReadDataW(ReadDataWfromDCache),
.ReadDataM(HPTWReadPTE), .ReadDataM(HPTWReadPTE),

65
wally-pipelined/src/lsu/lsuArb.sv
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@ -30,46 +30,47 @@ module lsuArb
(input logic clk, reset, (input logic clk, reset,
// from page table walker // from page table walker
input logic SelPTW, input logic SelPTW,
input logic HPTWRead, input logic HPTWRead,
input logic [`XLEN-1:0] HPTWPAdrE, input logic [`PA_BITS-1:0] TranslationPAdrE,
output logic HPTWStall, output logic HPTWStall,
// from CPU // from CPU
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
input logic [1:0] AtomicM, input logic [1:0] AtomicM,
input logic [`XLEN-1:0] MemAdrM, input logic [`XLEN-1:0] MemAdrM,
input logic [`XLEN-1:0] MemAdrE, input logic [`XLEN-1:0] MemAdrE,
input logic StallW, input logic StallW,
input logic PendingInterruptM, input logic PendingInterruptM,
// to CPU // to CPU
output logic [`XLEN-1:0] ReadDataW, output logic [`XLEN-1:0] ReadDataW,
output logic DataMisalignedM, output logic DataMisalignedM,
output logic CommittedM, output logic CommittedM,
output logic LSUStall, output logic LSUStall,
// to D Cache // to D Cache
output logic DisableTranslation, output logic DisableTranslation,
output logic [1:0] MemRWMtoLRSC, output logic [1:0] MemRWMtoLRSC,
output logic [2:0] Funct3MtoDCache, output logic [2:0] Funct3MtoDCache,
output logic [1:0] AtomicMtoDCache, output logic [1:0] AtomicMtoDCache,
output logic [`XLEN-1:0] MemAdrMtoDCache, output logic [`PA_BITS-1:0] MemPAdrMtoDCache,
output logic [`XLEN-1:0] MemAdrEtoDCache, output logic [11:0] MemAdrEtoDCache,
output logic StallWtoDCache, output logic StallWtoDCache,
output logic PendingInterruptMtoDCache, output logic PendingInterruptMtoDCache,
// from D Cache // from D Cache
input logic CommittedMfromDCache, input logic CommittedMfromDCache,
input logic DataMisalignedMfromDCache, input logic DataMisalignedMfromDCache,
input logic [`XLEN-1:0] ReadDataWfromDCache, input logic [`XLEN-1:0] ReadDataWfromDCache,
input logic DCacheStall input logic DCacheStall
); );
logic [2:0] PTWSize; logic [2:0] PTWSize;
logic [`XLEN-1:0] HPTWPAdrM; logic [`PA_BITS-1:0] TranslationPAdrM;
logic [`XLEN+1:0] MemAdrMExt;
// multiplex the outputs to LSU // multiplex the outputs to LSU
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
@ -80,11 +81,13 @@ module lsuArb
endgenerate endgenerate
mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache); mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); // delay HPTWPAdr by a cycle // this is for the d cache SRAM.
flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM); // delay TranslationPAdrM by a cycle
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM; // *** DH: I don't understand this logic 7/18/21. Why should PCF ever go here? assign MemAdrMExt = {2'b00, MemAdrM};
assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE; assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0];
assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : MemAdrE[11:0];
assign StallWtoDCache = SelPTW ? 1'b0 : StallW; assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
// always block interrupts when using the hardware page table walker. // always block interrupts when using the hardware page table walker.
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;

7
wally-pipelined/src/mmu/hptw.sv
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@ -43,9 +43,7 @@ module hptw
output logic [1:0] PageType, // page type to TLBs output logic [1:0] PageType, // page type to TLBs
output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
output logic SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU output logic SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU
output logic [`XLEN-1:0] TranslationVAdr,
output logic [`PA_BITS-1:0] TranslationPAdr, output logic [`PA_BITS-1:0] TranslationPAdr,
output logic UseTranslationVAdr,
output logic HPTWRead, // HPTW requesting to read memory output logic HPTWRead, // HPTW requesting to read memory
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
); );
@ -64,6 +62,8 @@ module hptw
logic PRegEn; logic PRegEn;
logic [1:0] NextPageType; logic [1:0] NextPageType;
logic [`SVMODE_BITS-1:0] SvMode; logic [`SVMODE_BITS-1:0] SvMode;
logic [`XLEN-1:0] TranslationVAdr;
typedef enum {LEVEL0_SET_ADR, LEVEL0_READ, LEVEL0, typedef enum {LEVEL0_SET_ADR, LEVEL0_READ, LEVEL0,
LEVEL1_SET_ADR, LEVEL1_READ, LEVEL1, LEVEL1_SET_ADR, LEVEL1_READ, LEVEL1,
@ -101,7 +101,6 @@ module hptw
assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT); assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk; assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk; assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
assign UseTranslationVAdr = (NextWalkerState == LEAF) || (WalkerState == LEAF); // ***explain this logic
// Raise faults. DTLBMiss // Raise faults. DTLBMiss
assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk; assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk;
@ -198,7 +197,7 @@ module hptw
end else begin // No Virtual memory supported; tie HPTW outputs to 0 end else begin // No Virtual memory supported; tie HPTW outputs to 0
assign HPTWRead = 0; assign SelPTW = 0; assign HPTWRead = 0; assign SelPTW = 0;
assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
assign TranslationVAdr = 0; assign TranslationPAdr = 0; assign UseTranslationVAdr = 0; assign TranslationPAdr = 0;
end end
endgenerate endgenerate
endmodule endmodule

20
wally-pipelined/src/mmu/mmu.sv
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@ -44,8 +44,16 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
// 11 - TLB is accessed for both read and write // 11 - TLB is accessed for both read and write
input logic DisableTranslation, input logic DisableTranslation,
// address input (could be virtual or physical) // VAdr goes to the TLB only. Virtual if the TLB is active.
input logic [`XLEN-1:0] Address, // PAdr goes to address mux bypassing the TLB. PAdr used when there is no translation.
// Comes from either the program address (instruction address or load/store address)
// or from the hardware pagetable walker.
// PAdr is intended to used as a phsycial address. Discarded by the address mux when translation is
// performed.
// PhysicalAddress is selected to be PAdr when no translation or the translated VAdr (TLBPAdr)
// when there is translation.
input logic [`PA_BITS-1:0] PAdr, // *** consider renaming this.
input logic [`XLEN-1:0] VAdr,
input logic [1:0] Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits input logic [1:0] Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
// Controls for writing a new entry to the TLB // Controls for writing a new entry to the TLB
@ -77,7 +85,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
); );
logic [`PA_BITS-1:0] TLBPAdr; logic [`PA_BITS-1:0] TLBPAdr;
logic [`XLEN+1:0] AddressExt;
logic PMPSquashBusAccess, PMASquashBusAccess; logic PMPSquashBusAccess, PMASquashBusAccess;
// Translation lookaside buffer // Translation lookaside buffer
@ -95,7 +102,9 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
assign WriteAccess = WriteAccessM; assign WriteAccess = WriteAccessM;
tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU))
tlb(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]), tlb(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
.SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .*); .SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]),
.VAdr,
.*);
end else begin // just pass address through as physical end else begin // just pass address through as physical
assign Translate = 0; assign Translate = 0;
@ -106,8 +115,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
endgenerate endgenerate
// If translation is occuring, select translated physical address from TLB // If translation is occuring, select translated physical address from TLB
assign AddressExt = {2'b00, Address}; // extend length of virtual address if necessary for RV32 mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
mux2 #(`PA_BITS) addressmux(AddressExt[`PA_BITS-1:0], TLBPAdr, Translate, PhysicalAddress);
/////////////////////////////////////////// ///////////////////////////////////////////
// Check physical memory accesses // Check physical memory accesses

9
wally-pipelined/src/mmu/tlb.sv
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@ -70,7 +70,7 @@ module tlb #(parameter TLB_ENTRIES = 8,
input logic DisableTranslation, input logic DisableTranslation,
// address input before translation (could be physical or virtual) // address input before translation (could be physical or virtual)
input logic [`XLEN-1:0] Address, input logic [`XLEN-1:0] VAdr,
// Controls for writing a new entry to the TLB // Controls for writing a new entry to the TLB
input logic [`XLEN-1:0] PTE, input logic [`XLEN-1:0] PTE,
@ -95,7 +95,6 @@ module tlb #(parameter TLB_ENTRIES = 8,
// Sections of the virtual and physical addresses // Sections of the virtual and physical addresses
logic [`VPN_BITS-1:0] VPN; logic [`VPN_BITS-1:0] VPN;
logic [`PPN_BITS-1:0] PPN; logic [`PPN_BITS-1:0] PPN;
logic [`XLEN+1:0] AddressExt;
// Sections of the page table entry // Sections of the page table entry
logic [7:0] PTEAccessBits; logic [7:0] PTEAccessBits;
@ -106,9 +105,9 @@ module tlb #(parameter TLB_ENTRIES = 8,
logic CAMHit; logic CAMHit;
logic SV39Mode; logic SV39Mode;
assign VPN = Address[`VPN_BITS+11:12]; assign VPN = VAdr[`VPN_BITS+11:12];
tlbcontrol tlbcontrol(.SATP_MODE, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, tlbcontrol tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
.PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault,
.SV39Mode, .Translate); .SV39Mode, .Translate);
@ -122,6 +121,6 @@ module tlb #(parameter TLB_ENTRIES = 8,
// Replace segments of the virtual page number with segments of the physical // Replace segments of the virtual page number with segments of the physical
// page number. For 4 KB pages, the entire virtual page number is replaced. // page number. For 4 KB pages, the entire virtual page number is replaced.
// For superpages, some segments are considered offsets into a larger page. // For superpages, some segments are considered offsets into a larger page.
tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Address(Address[11:0]), .TLBHit, .TLBPAdr); tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr);
endmodule endmodule

6
wally-pipelined/src/mmu/tlbcontrol.sv
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@ -31,7 +31,7 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
// Current value of satp CSR (from privileged unit) // Current value of satp CSR (from privileged unit)
input logic [`SVMODE_BITS-1:0] SATP_MODE, input logic [`SVMODE_BITS-1:0] SATP_MODE,
input logic [`XLEN-1:0] Address, input logic [`XLEN-1:0] VAdr,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
@ -70,8 +70,8 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
assign SV39Mode = (SATP_MODE == `SV39); assign SV39Mode = (SATP_MODE == `SV39);
// generate page fault if upper bits aren't all the same // generate page fault if upper bits aren't all the same
logic UpperEqual39, UpperEqual48; logic UpperEqual39, UpperEqual48;
assign UpperEqual39 = &(Address[63:38]) | ~|(Address[63:38]); assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
assign UpperEqual48 = &(Address[63:47]) | ~|(Address[63:47]); assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48; assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
end else begin end else begin
assign SV39Mode = 0; assign SV39Mode = 0;

4
wally-pipelined/src/mmu/tlbmixer.sv
View File

@ -32,7 +32,7 @@ module tlbmixer (
input logic [`VPN_BITS-1:0] VPN, input logic [`VPN_BITS-1:0] VPN,
input logic [`PPN_BITS-1:0] PPN, input logic [`PPN_BITS-1:0] PPN,
input logic [1:0] HitPageType, input logic [1:0] HitPageType,
input logic [11:0] Address, input logic [11:0] Offset,
input logic TLBHit, input logic TLBHit,
output logic [`PA_BITS-1:0] TLBPAdr output logic [`PA_BITS-1:0] TLBPAdr
); );
@ -63,6 +63,6 @@ module tlbmixer (
//assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask); //assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask);
// Output the hit physical address if translation is currently on. // Output the hit physical address if translation is currently on.
// Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Address[11:0]}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
endmodule endmodule