diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index bbbda2f46..a55b32987 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -260,15 +260,13 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/RawFlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/OldFlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntRst add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} @@ -601,7 +599,7 @@ add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayCntEn TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {408937 ns} 0} {{Cursor 4} {329828 ns} 1} {{Cursor 5} {408936 ns} 1} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {329696 ns} 0} {{Cursor 4} {329828 ns} 1} {{Cursor 5} {408936 ns} 1} quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -617,4 +615,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {408747 ns} {409125 ns} +WaveRestoreZoom {329508 ns} {329874 ns} diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 36946c26c..f20fd42eb 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -77,7 +77,7 @@ module cachefsm logic AMO, StoreAMO; logic AnyUpdateHit, AnyHit; logic AnyMiss; - logic FlushFlag, FlushWayAndNotAdrFlag; + logic FlushFlag; typedef enum logic [3:0] {STATE_READY, // hit states // miss states @@ -87,8 +87,6 @@ module cachefsm STATE_MISS_READ_DELAY, // required for back to back reads. structural hazard on writting SRAM // flush cache STATE_FLUSH, - STATE_FLUSH_CHECK, - STATE_FLUSH_INCR, STATE_FLUSH_WRITE_BACK} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; @@ -140,20 +138,6 @@ module cachefsm STATE_FLUSH_WRITE_BACK: if(CacheBusAck & ~(FlushFlag & FlushWayFlag)) NextState = STATE_FLUSH; else if(CacheBusAck) NextState = STATE_READY; else NextState = STATE_FLUSH_WRITE_BACK; - -/* -----\/----- EXCLUDED -----\/----- - STATE_FLUSH: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_CHECK: if(LineDirty) NextState = STATE_FLUSH_WRITE_BACK; - else if(FlushFlag) NextState = STATE_READY; - else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_WRITE_BACK: if(CacheBusAck) begin - if(FlushFlag) NextState = STATE_READY; - else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - end else NextState = STATE_FLUSH_WRITE_BACK; - -----/\----- EXCLUDED -----/\----- */ default: NextState = STATE_READY; endcase end @@ -180,11 +164,10 @@ module cachefsm // Flush and eviction controls assign SelWriteback = (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | (CurrState == STATE_READY & AnyMiss & LineDirty); - assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | - (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK); - assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag; - //assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~LineDirty & FlushWayAndNotAdrFlag) | - // (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayAndNotAdrFlag & CacheBusAck); + + assign SelFlush = (CurrState == STATE_READY & FlushCache) | + (CurrState == STATE_FLUSH & ~FlushFlag) | + (CurrState == STATE_FLUSH_WRITE_BACK & ~(CacheBusAck & FlushFlag)); assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayFlag & CacheBusAck) | (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) | @@ -195,13 +178,9 @@ module cachefsm assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) | (CurrState == STATE_MISS_EVICT_DIRTY & CacheBusAck); -// assign CacheBusRW[1] = CurrState == STATE_READY & AnyMiss; assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | - (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) | - (CurrState == STATE_FLUSH_CHECK & LineDirty); -// assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & LineDirty) | -// (CurrState == STATE_FLUSH_CHECK & VictimDirty); + (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck); // **** can this be simplified? assign SelAdr = (CurrState == STATE_READY & ((StoreAMO) & CacheHit)) | // changes if store delay hazard removed (CurrState == STATE_READY & (AnyMiss)) |