diff --git a/bin/regression-wally b/bin/regression-wally index 09bd1fa9c..800d0dd82 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -397,6 +397,7 @@ parser.add_argument("--nightly", help="Run large nightly regression", action="st parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used +parser.add_argument("--breker", help="Run Breker tests", action="store_true") parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") args = parser.parse_args() @@ -441,7 +442,8 @@ elif (args.fcov): # run tests in lockstep in functional coverage mode addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim) addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim) - +# elif (args.breker): +# addLockstepTestsByDir(WALLY+"/tests/breker/work", "breker", coveragesim, 0) else: for sim in sims: if (not (args.buildroot and sim == lockstepsim)): # skip short buildroot sim if running long one diff --git a/bin/wsim b/bin/wsim index 91f8e30ab..a6bb89b72 100755 --- a/bin/wsim +++ b/bin/wsim @@ -50,6 +50,9 @@ def validateArgs(args): elif (args.tb == "testbench_fp" and args.sim != "questa"): print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench") exit(1) + elif ("breker" in args.elf or "breker" in args.testsuite) and args.sim != "questa": + print("Error: Breker tests currently only supported by Questa") + exit(1) def elfFileCheck(args): ElfFile = "" @@ -90,6 +93,8 @@ def prepSim(args, ElfFile): flags += " --ccov" if args.fcov: flags += " --fcov" + if "breker" in ElfFile: + flags += " --breker" prefix, suffix = lockstepSetup(args) flags += suffix return flags, prefix diff --git a/sim/questa/wally.do b/sim/questa/wally.do index f42bf4930..2a0fcb052 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -37,6 +37,7 @@ onerror {quit -f} # Initialize variables set CFG ${1} set TESTSUITE ${2} +set TESTSUITE_NO_ELF [file rootname ${TESTSUITE}] set TESTBENCH ${3} set WKDIR wkdir/${CFG}_${TESTSUITE} set WALLY $::env(WALLY) @@ -62,11 +63,17 @@ set CoverageVsimArg "" set FunctCoverage 0 set FCvlog "" -set FCvopt "" +set FCvsim "" set FCdefineCOVER_EXTS {} +set breker 0 +set brekervlog "" +set brekervopt "" +set brekervsim "" + set lockstep 0 set lockstepvlog "" + set SVLib "" set GUI 0 @@ -107,13 +114,11 @@ if {[lcheck lst "--ccov"]} { if {[lcheck lst "--fcov"]} { set FunctCoverage 1 # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests - set FCvlog "+define+INCLUDE_TRACE2COV \ + set FCvlog "+define+INCLUDE_TRACE2COV \ +define+IDV_INCLUDE_TRACE2COV \ +define+COVER_BASE_RV32I \ - +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ - " - set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" - + +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source" + set FCvsim "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" } # if --lockstep or --fcov found set flag and remove from list @@ -124,7 +129,20 @@ if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" - set SVLib "-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model" + set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " +} + +# if --breker found set flag and remove from list +if {[lcheck lst "--breker"]} { + set breker 1 + set BREKER_HOME $::env(BREKER_HOME) + set brekervlog "+define+USE_TREK_DV \ + +incdir+${WALLY}/testbench/trek_files \ + ${WALLY}/testbench/trek_files/uvm_output/trek_uvm_pkg.sv" + set brekervopt "${WKDIR}.trek_uvm" + # may need to change this path + set brekervsim "+TREK_TBX_FILE=${WALLY}/tests/breker/work/${TESTSUITE_NO_ELF}/${TESTSUITE_NO_ELF}.tbx" + append SVLib " -sv_lib ${BREKER_HOME}/linux64/lib/libtrek " } # Set PlusArgs passed using the --args flag @@ -151,6 +169,7 @@ if {$DEBUG > 0} { echo "ccov = $ccov" echo "lockstep = $lockstep" echo "FunctCoverage = $FunctCoverage" + echo "Breker = $breker" echo "remaining list = $lst" echo "Extra +args = $PlusArgs" echo "Extra -args = $ExpandedParamArgs" @@ -162,13 +181,13 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg} +vopt $accFlag ${WKDIR}.${TESTBENCH} ${brekervopt} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg} -vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} {*}${FCvopt} -suppress 3829 ${CoverageVsimArg} +vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} {*}${FCvsim} {*}${brekervsim} -suppress 3829 ${CoverageVsimArg} # power add generates the logging necessary for saif generation. # power add -r /dut/core/* diff --git a/site-setup.sh b/site-setup.sh index 4699ff348..81f17fff2 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -15,6 +15,7 @@ export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change thi export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys DC, excluding bin export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin +export BREKER_HOME=/cad/breker/trek5-2.1.10b-GCC6_el7 # Change this for your path to Breker Trek # Tools # Questa and Synopsys diff --git a/testbench/testbench.sv b/testbench/testbench.sv index c777fdf3f..312467a33 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -45,6 +45,13 @@ module testbench; parameter D_CACHE_ADDR_LOGGER=0; parameter RVVI_SYNTH_SUPPORTED=0; + `ifdef USE_TREK_DV + event trek_start; + always @(testbench.trek_start) begin + trek_uvm_pkg::trek_uvm_events::do_backdoor_init(); + end + `endif + `ifdef USE_IMPERAS_DV import idvPkg::*; import rvviApiPkg::*; @@ -518,6 +525,10 @@ module testbench; end else begin $fclose(uncoreMemFile); $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM); + `ifdef USE_TREK_DV + -> trek_start; + $display("starting Trek...."); + `endif end end if (TEST == "embench") $display("Read memfile %s", memfilename); diff --git a/testbench/trek_files/Makefile b/testbench/trek_files/Makefile new file mode 100644 index 000000000..02c9b6f56 --- /dev/null +++ b/testbench/trek_files/Makefile @@ -0,0 +1,12 @@ +TREKFILES := $(WALLY)/testbench/trek_files +PLATFORM_YAML := $(TREKFILES)/platform.yaml +TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml +TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation +TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) + +uvm_output: + rm -rf uvm_output + $(TREKSVIP) -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) --uvm_output=uvm_output + +clean: + rm -rf uvm_output diff --git a/testbench/trek_files/breker-setup.sh b/testbench/trek_files/breker-setup.sh new file mode 100644 index 000000000..9b651eeef --- /dev/null +++ b/testbench/trek_files/breker-setup.sh @@ -0,0 +1,5 @@ +#!/bin/bash +export BREKER_ARCH=${BREKER_HOME}/linux64 +export PATH=${BREKER_HOME}/bin:${BREKER_HOME}/examples/tutorials/apps/coherency/bin:${PATH} +export LD_LIBRARY_PATH=".:${BREKER_ARCH}/lib:${BREKER_HOME}/opensrc/gcc/lib:${BREKER_HOME}/opensrc/gcc/lib64":${LD_LIBRARY_PATH} +export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu/:$LIBRARY_PATH diff --git a/testbench/trek_files/customer.yaml b/testbench/trek_files/customer.yaml new file mode 100644 index 000000000..e06733797 --- /dev/null +++ b/testbench/trek_files/customer.yaml @@ -0,0 +1,27 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 5 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + # uncomment the `weights:` line below if any entries under `weights:` need to be enabled + # weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + + diff --git a/testbench/trek_files/platform.yaml b/testbench/trek_files/platform.yaml new file mode 100644 index 000000000..16b1da612 --- /dev/null +++ b/testbench/trek_files/platform.yaml @@ -0,0 +1,258 @@ +trek: + platform_config: + doc: >- + Testbench platform specific configuration. + processors: + doc: >- + Information about available processors. + processor_count: + value: 1 + doc: >- + How many processors can be used by the generated test case + sw_threads_per_processor: + value: 2 + doc: >- + How many software threads to put on each processor + tlm_generic_ports: + doc: >- + Information about available tlm_generic_payload ports + port_count: + value: 0 + doc: >- + How many tlm ports to use for memory operations + threads_per_port: + value: 4 + doc: >- + How many threads to put on each tlm port + debug: + value: 1 + doc: >- + Turn on for verbose tlm port messages + memories: + doc: >- + Information about memory regions that can be used by the generated test case. + defaults: + doc: >- + Default values for all memories + natural_alignment: + value: 1 + doc: >- + Should all memory addresses be naturally aligned (up to 8 byte alignment) + init_type: + value: frontdoor + doc: >- + Strategy to use for memory initialization. + Options are: + - static + - backdoor + - frontdoor + memory: + doc: >- + Define a memory region. + Multiple memory regions may be defined in this section. + name: + value: ddr0 + doc: >- + Name of the memory region + base: + value: 0x82000000 + doc: >- + Base address of memory region. + Ignored for `static` initialized memory + size: + value: 0x100000 + doc: >- + Size of memory region in bytes. + init_type: + value: backdoor #frontdoor + doc: >- + Strategy to use for memory initialization. + Options are: + - static + - backdoor + - frontdoor + caches: + doc: >- + parameters related to cache architecture + cache_line_size: + value: 64 + doc: >- + Size of a cache line in bytes + llc_cache_size: + value: 0x200000 + doc: >- + size of last level cache in bytes + llc_cache_ways: + value: 8 + doc: >- + number of ways in the last level cache + mailbox: + doc: >- + Configure memory mailbox usage + type: + value: single + doc: >- + Configure mailbox type. + Options are: + - single: for use by TrekBox with backdoor access + - queue: for use in post-silicon post-process flow + single: + doc: >- + Detail settings when mailbox type is `single` + init_type: + value: static + doc: >- + Strategy to use for mailbox memory initialization. + Options are: + - static + - backdoor + - frontdoor + c2t_base: + value: 0x1000 + doc: >- + Fixed base address of C to trekbox mailbox region. + Allow 64 bytes per processor. + Used for init_type of `backdoor` and `frontdoor` only. + t2c_base: + value: 0x2000 + doc: >- + Fixed base address of trekbox to C mailbox region. + Allow 64 bytes per processor. + Used for init_type of `backdoor` and `frontdoor` only. + cacheable: + value: 1 + doc: >- + Set this parameter to 1 to do a cache flush after every mailbox + write. + queue: + doc: >- + Detail settings when mailbox type is `queue` + length: + value: 1000 + doc: >- + Max number of messages that can be stored in the queue mailbox. + Longer tests may need a larger queue. + debug: + value: 0 + doc: >- + If this flag is set to 1, messages will be printed directly to the + console instead of being queued in memory. + stdio: + doc: >- + Is the standard library available for use by the generated test. + available: + value: 0 + doc: >- + Set this value to 0 of the library is not available in + your system. + use_lock: + value: 1 + doc: >- + Calls to console print messages will be mutex locked unless + this flag is set to 0. + header: + doc: >- + Verbatim code that will be put into the header section of the test. + value: |- + + declaration: + doc: >- + Verbatim code that will be put into the declaration section of the test. + value: |- + int main(void) + { + return trek_main(); + } + + mmu: # Trek can generate code to program page/translation tables + # that you MAY want to use with your SDV generated C files. + # Here, you have some control over that process. + + va_bits: 39 # How many bits are used for virtual addresses + # + # For aarch64, the value here is used to determine the + # "initial lookup level" (as detailed in Table D5-13). + # This must correlate to TCR_EL3.T0SZ! + # + # For riscv64, only 39, 48, and 57 are supported + # corresponding to "Sv39", "Sv48", and "Sv57". + # + # default: 39 [from T0SZ=64-39=25(0x19)] + + memory_map: # A *MAP* of all memory regions, excluding the + # memory_resources in your platformConfig.h file. + # + # Each map entry should be a unique name. + # + # Mandatory submap pairs: + # normal: *true*/false (false = "device"/"io" memory) + # begin: starting address + # end: ending address + # + # Optional submap pairs: + # readable: *true*/false + # writeable: *true*/false + # executable: true/*false* + # cacheable: *true*/false (*false* for device) + # share_type (aarch64 only): *inner-shareable*, + # outer-shareable, non-shareable + # + # Note that memory_resources will use all defaults. + # + # Note that "normal: false" (device-memory) change defaults + # to "cacheable = false", and on arch64 it implies + # share_type = non-shareable, and alloc_type = no-allocate + + UART0: + type: device + begin: 0x10000000 + end: 0x10000fff + + code: + type: normal + begin: 0x80000000 + end: 0x807fffff + executable: true + + stack: + type: normal + begin: 0x87000000 + end: 0x87ffffff + + + aarch64: # Customizations that are only valid for aarch64. + + TCR_EL3: 0x80923519 # Should Trek to program the TCR_TL3 register? If + # so, put the value here. If not, comment out + # this option. + # NOTE: T0SZ should correlate to va_bits above! + # default: -no default- + + allocate_type: read-write-allocate # Default allocate_type. + # read-allocate, write-allocate, + # *read-write-allocate*, no-allocate + + cache_type: write-back-nontransient # non-cacheable, + # write-through-transient, + # write-back-transient, + # write-through-non-transient, + # *write-back-non-transient* + + device_type: nGnRnE # *nGnRnE*, nGnRE, nGRE, GRE + + share_type: inner-shareable # non-shareable + # inner-shareable + # outer-shareable + + riscv64: # Customizations that are only valid for riscv64. + + Svnapot: false # If standard extension "Svnapot" is implemented, and + # when you are using Sv39, you might set this to "true" + # to allow PTE bit[63] "N" to be set when appropriate. + # default: false + + Svpbmt: true # If standard extension "Svpbmt" is implemented, and + # when you are using Sv39, you might set this to "true" + # to allow cacheable/device information to flow into + # bits[62:61] "PBMT" as appropriate. + # default: false diff --git a/testbench/trek_files/trek_user_backdoor.sv b/testbench/trek_files/trek_user_backdoor.sv new file mode 100644 index 000000000..342ade7b9 --- /dev/null +++ b/testbench/trek_files/trek_user_backdoor.sv @@ -0,0 +1,91 @@ +/// custom routines defined for the platform + +// Design parameters, used in the code below and custom to this design! +//`define RAM_PATH soc_top.soc_instance.i_sram_subsystem.i_shared_ram +//sim:/testbench/dut/uncore/uncore/ram/ram/memory/RAM +//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory.RAM +//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory +`define RAM_PATH testbench.dut.uncoregen.uncore.ram.ram.memory.ram +//`define RAM_BASE_ADDR 32'h80000000 +`define RAM_BASE_ADDR testbench.P.UNCORE_RAM_BASE + +// These two routines are specific to a particular design. They are used +// to read and write to the "mailbox" locations, to synchronize behaviors +// between C code on the processors with activity performed in UVM (and +// among activities in UVM). +// +// Every design will be different. Here we just have a simple Verilog +// array that we can read and write. +// +function automatic void trek_backdoor_read64( + input longint unsigned address, + output longint unsigned data, + input int unsigned debug = 1); + + //bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2; + bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8)); + if (address[1:0] != 2'b00) begin: misaligned + $display("%t trek_backdoor_read64: Misaligned address", $time); + $finish(); + end + + //data[63:32] = `RAM_PATH[offset + 0]; + //data[31: 0] = `RAM_PATH[offset + 1]; + data[63:0] = `RAM_PATH.RAM[offset + 0]; +if (data != 0) + $display("%t trek_backdoor_read64: Read 64'h%016h from address 64'h%016h", + $time, data, address); +endfunction: trek_backdoor_read64 + + +function automatic void trek_backdoor_write64( + input longint unsigned address, + input longint unsigned data, + input int unsigned debug = 1); + + //bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2; + bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8)); + + if (address[1:0] != 2'b00) begin: misaligned + $display("%t trek_backdoor_write64: Misaligned address", $time); + $finish(); + end + //`RAM_PATH[offset + 0] = data[63:32]; + //`RAM_PATH[offset + 1] = data[31: 0]; + `RAM_PATH.RAM[offset + 0] = data[63:0]; + //$display("%t trek_backdoor_write64: Wrote 64'h%016h to address 64'h%016h", + //$time, data, address); +endfunction: trek_backdoor_write64 + + +// For performance, we want to read mailboxes ONLY when they're written to! +// (This is very important on emulators!) +// +// Here we trigger a signal when a memory write happens to the range of +// addresses where the mailboxes are. +// +// A clock later, we go poll all the mailboxes (using the "backdoor_read" +// method above. +// +// Each design will be different, depending on where you are able to snoop +// for writes and how long it takes a write to propagate from that point +// to the place where the backdoor read will find it. + +bit trek_c2t_mbox_event; +bit trek_is_event_addr; + +//assign trek_is_event_addr = +// ((((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) >= `TREK_C2T_MBOX_BASE) && +// (((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) < `TREK_C2T_MBOX_LIMIT)); +// +//always_ff @(posedge `RAM_PATH.clk) begin: trigger_reading_of_mailboxes +// trek_c2t_mbox_event <= (trek_is_event_addr && +// (`RAM_PATH.n_cs == 1'b0) && +// (`RAM_PATH.n_we == 1'b0)); +//end + +// Design specifc: one stage delayed so write has a time to settle +//always @(posedge trek_c2t_mbox_event) begin: read_all_mailboxes +always @(posedge testbench.clk) begin: read_all_mailboxes + trek_poll_mbox(); +end diff --git a/tests/breker/Makefile b/tests/breker/Makefile new file mode 100644 index 000000000..bd21b8b22 --- /dev/null +++ b/tests/breker/Makefile @@ -0,0 +1,56 @@ +shell := /bin/bash + +# Breker/Trek paths and variables +TESTDIR := $(WALLY)/tests/breker/work +TREKFILES := $(WALLY)/testbench/trek_files +CONSTRAINTS_DIR := $(WALLY)/tests/breker/constraints +PLATFORM_YAML := $(TREKFILES)/platform.yaml +CUSTOMER_YAML := $(TREKFILES)/customer.yaml +TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml +CONSTRAINT_FILES := $(shell find $(CONSTRAINTS_DIR) -type f) +TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation +TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS) + +# Compilation paths and variables +MARCH :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval +MABI :=-mabi=lp64d +LINKER := $(WALLY)/tests/custom/linker8000-0000.x +LINK_FLAGS := -nostartfiles +CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU +CRT0_DIR := $(WALLY)/tests/custom/crt0 +WIDTH := 64 + +# Find all constraint files and generate tests for each one +TESTS = $(patsubst $(CONSTRAINTS_DIR)/%.yaml,$(TESTDIR)/%,$(CONSTRAINT_FILES)) +.PHONY: all clean +all: $(TESTS) + +# Generate c tests +$(TESTDIR)/%: $(CONSTRAINTS_DIR)/%.yaml | $(TESTDIR) + $(TREKSVIP) -p $< -p $(CUSTOMER_YAML) -o $@/$* -e pss_top.entry + $(MAKE) $@/$*.elf.memfile + +# Compile c code +.PRECIOUS: %.elf +%.elf: %.c $(CRT0_DIR)/libcrt0.a + riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -g -o $@ $< -L$(CRT0_DIR) -lcrt0 -T $(LINKER) > /dev/null + +# Convert elf to hex +%.elf.memfile: %.elf + riscv64-unknown-elf-objdump -D $< > $<.objdump + riscv64-unknown-elf-elf2hex --bit-width $(WIDTH) --input $< --output $@ + extractFunctionRadix.sh $<.objdump + +# View the model graph TODO: What does this do? Move to another makefile? +%.view_graph:% + $(TREKSVIP) -p ../tests/test_$^.yaml -p $(CUSTOMER_YAML) -t pss_top.entry + +# Library needed for C code +$(CRT0_DIR)/libcrt0.a: + make -C $(CRT0_DIR) + +$(TESTDIR): + mkdir -p $(TESTDIR) + +clean: + rm -rf $(TESTS) diff --git a/tests/breker/constraints/atomics.yaml b/tests/breker/constraints/atomics.yaml new file mode 100644 index 000000000..c505b957d --- /dev/null +++ b/tests/breker/constraints/atomics.yaml @@ -0,0 +1,73 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + pss_top.dekker.dekkerTest: 0 + # pss_top.atomics.atomicsTest: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/coherency.yaml b/tests/breker/constraints/coherency.yaml new file mode 100644 index 000000000..62908c90c --- /dev/null +++ b/tests/breker/constraints/coherency.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/dekker.yaml b/tests/breker/constraints/dekker.yaml new file mode 100644 index 000000000..052c7e02d --- /dev/null +++ b/tests/breker/constraints/dekker.yaml @@ -0,0 +1,73 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + # pss_top.dekker.dekkerTest: 0 + pss_top.atomics.atomicsTest: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/hello.yaml b/tests/breker/constraints/hello.yaml new file mode 100644 index 000000000..94b30664d --- /dev/null +++ b/tests/breker/constraints/hello.yaml @@ -0,0 +1,58 @@ +# Constraint file to generate simple hello world test that checks the +# initialized values for a few memory locations. + +# This constraint file disable all features other than the +trek: + svip: + global: + scenarios: + scenario_count: + # reduce number of scenarios + value: 2 + memory_allocation: + memory_sets: + block_size: + # force 4 byte operation + min: 4 + max: 4 + block_count: + # force a single memory block + min: 1 + max: 1 + riscv: + extensions: + # disable hypervisor extension + # if your system does not support this feature + h_hypervisor: + value: 0 + coherency: + cacheline_states: + scenario_length: + # minimize scenario length + min: 1 + max: 1 + weights: + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off memory workload tests + # pss_top.workload.entry: 0 + + # turn of various cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of micro loop feature + pss_top.microLoops.microLoopScn: 0 + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + diff --git a/tests/breker/constraints/microloops.yaml b/tests/breker/constraints/microloops.yaml new file mode 100644 index 000000000..b8502b0f6 --- /dev/null +++ b/tests/breker/constraints/microloops.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/mmu.yaml b/tests/breker/constraints/mmu.yaml new file mode 100644 index 000000000..2b2dbac44 --- /dev/null +++ b/tests/breker/constraints/mmu.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + # pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/riscv.yaml b/tests/breker/constraints/riscv.yaml new file mode 100644 index 000000000..7e8a6c0d1 --- /dev/null +++ b/tests/breker/constraints/riscv.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + # pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + # pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/test.yaml b/tests/breker/constraints/test.yaml new file mode 100644 index 000000000..fdf3e294b --- /dev/null +++ b/tests/breker/constraints/test.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + # weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + # pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + # pss_top.soc: 0 + + + # turn off RV64 opcode tests + # pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + # pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + # pss_top.readOnly.entry: 0 + # pss_top.writeOnly.entry: 0 + # pss_top.writeRead.entry: 0 + # pss_top.readWrite.entry: 0 + # pss_top.moesiStates.entry: 0 + # pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + # pss_top.microLoops.microLoopScn: 0 diff --git a/tests/breker/constraints/workload.yaml b/tests/breker/constraints/workload.yaml new file mode 100644 index 000000000..61f641ea5 --- /dev/null +++ b/tests/breker/constraints/workload.yaml @@ -0,0 +1,72 @@ +trek: + svip: + global: + scenarios: + scenario_count: + # primary control for length of test + value: 10 + riscv: + extensions: + # disable hypervisor extension by setting value to 0 + # if your system does not support this feature + h_hypervisor: + value: 0 + + weights: + # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System + # if your system does not support this feature + # pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0 + + # qemu-riscv64 does not ignore writes to WARL bits in hgatp + # Comment out the next line unless your design has this issue + # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0 + + + # turn off MMU Tests + pss_top.rvMmu.rvMmuOp: 0 + + # turn off rvMmu Self-modifying-code (SMC) scenarios + # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0 + + # turn off rvMmuOp page fault cases + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0 + # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0 + + # turn of SoC level Dekker and Atomics tests + pss_top.soc: 0 + + + # turn off RV64 opcode tests + pss_top.rv64.rv64Ops: 0 + + # turn off software interrupts + pss_top.rvMswi.rvMswiOp: 0 + + + # turn off all coherency tests + # pss_top.coherency: 0 + + # turn off coherency memory workload tests + # pss_top.workload.entry: 0 + + # turn of various coherency cache state tests + pss_top.readOnly.entry: 0 + pss_top.writeOnly.entry: 0 + pss_top.writeRead.entry: 0 + pss_top.readWrite.entry: 0 + pss_top.moesiStates.entry: 0 + pss_top.tilelinkStates.entry: 0 + + # turn of coherency micro loop feature + # these scenarios take a while to run + pss_top.microLoops.microLoopScn: 0