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Cleaned up tlb output muxing

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David Harris 2021-07-06 10:44:05 -04:00
parent d58cad89a8
commit 30fdd7abc8
1 changed files with 1 additions and 2 deletions
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wally-pipelined/src/mmu/tlb.sv
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@ -135,7 +135,6 @@ module tlb #(parameter TLB_ENTRIES = 8,
// Output the hit physical address if translation is currently on. // Output the hit physical address if translation is currently on.
// Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
assign VAExt = {2'b00, VirtualAddress}; // extend length of virtual address if necessary for RV32 assign VAExt = {2'b00, VirtualAddress}; // extend length of virtual address if necessary for RV32
assign PageOffset = VirtualAddress[11:0]; mux2 #(`PA_BITS) hitmux('0, {PhysicalPageNumberMixed, VirtualAddress[11:0]}, TLBHit, PhysicalAddressFull); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
assign PhysicalAddressFull = TLBHit ? {PhysicalPageNumberMixed, PageOffset} : '0; // *** in block diagram TLB just works on page numbers
mux2 #(`PA_BITS) addressmux(VAExt[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress); mux2 #(`PA_BITS) addressmux(VAExt[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress);
endmodule endmodule