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https://github.com/openhwgroup/cvw
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removed duplicate quotient mux
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61230c967c
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@ -102,14 +102,12 @@ module fdivsqrtpostproc(
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if (`IDIV_ON_FPU) begin
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if (`IDIV_ON_FPU) begin
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logic [`DIVBLEN:0] NormShiftM;
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logic [`DIVBLEN:0] NormShiftM;
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logic [`DIVb:0] NormQuotM;
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logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM;
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logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM;
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assign W = $signed(Sum) >>> `LOGR;
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assign W = $signed(Sum) >>> `LOGR;
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assign DM = {4'b0001, D};
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assign DM = {4'b0001, D};
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// Integer division: sign handling for div and rem
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// Integer remainder: sticky and sign correction muxes
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mux2 #(`DIVb+1) normquotmux(FirstU, FirstUM, NegStickyM, NormQuotM);
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mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
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mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
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mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
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mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
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@ -129,7 +127,7 @@ module fdivsqrtpostproc(
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IntRemM = '0;
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IntRemM = '0;
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end
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end
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end else begin
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end else begin
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PreIntQuotM = {3'b000, NormQuotM};
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PreIntQuotM = {3'b000, PreQmM};
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IntRemM = NormRemM;
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IntRemM = NormRemM;
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end
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end
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// flip sign if necessary
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// flip sign if necessary
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@ -147,7 +145,7 @@ module fdivsqrtpostproc(
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end
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end
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// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
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// integer division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
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assign PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM);
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assign PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM);
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assign SpecialFPIntDivResultM = BZeroM ? (RemOpM ? AM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases
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assign SpecialFPIntDivResultM = BZeroM ? (RemOpM ? AM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases
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