From d5c1ac4e110f05274e61b6f81e96f0ff98d98985 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 22:03:51 -0600 Subject: [PATCH 1/6] Minor optimization to btb. --- pipelined/src/ifu/bpred/bpred.sv | 1 + pipelined/src/ifu/bpred/btb.sv | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 048aa1125..9889607a4 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -149,6 +149,7 @@ module bpred ( .PredValidF, .PredictionInstrClassWrongE, .IEUAdrE, + .InstrClassD, .InstrClassE); // the branch predictor needs a compact decoding of the instruction class. diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index 02c77fab9..dc32d9145 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -41,6 +41,7 @@ module btb #(parameter int Depth = 10 ) ( // update input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassD, // Instruction class to insert into btb input logic [3:0] InstrClassE // Instruction class to insert into btb ); @@ -71,7 +72,7 @@ module btb #(parameter int Depth = 10 ) ( assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - assign MatchF = PCNextFIndex == PCFIndex; + assign MatchF = PCNextFIndex == PCFIndex & PredValidF; assign MatchD = PCNextFIndex == PCDIndex; assign MatchE = PCNextFIndex == PCEIndex; assign MatchNextX = MatchF | MatchD | MatchE; @@ -79,7 +80,7 @@ module btb #(parameter int Depth = 10 ) ( flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {PredInstrClassD, PredPCD} : + MatchD ? {InstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); @@ -104,6 +105,6 @@ module btb #(parameter int Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); + flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); endmodule From 6fb624950ec1da1f4cc83d8b943907583b6cd684 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 00:24:54 -0600 Subject: [PATCH 2/6] Minor change to btb. --- pipelined/src/ifu/bpred/btb.sv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index dc32d9145..7cf9ed993 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -50,12 +50,12 @@ module btb #(parameter int Depth = 10 ) ( logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic [`XLEN-1:0] ResetPC; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; - logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; + logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; logic [`XLEN-1:0] PredPCD; logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; - logic TablePredValidF; + logic TablePredValidF, PredValidD; // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. @@ -72,20 +72,20 @@ module btb #(parameter int Depth = 10 ) ( assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - assign MatchF = PCNextFIndex == PCFIndex & PredValidF; + assign MatchF = PCNextFIndex == PCFIndex; assign MatchD = PCNextFIndex == PCDIndex; assign MatchE = PCNextFIndex == PCEIndex; assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {InstrClassD, PredPCD} : - {InstrClassE, IEUAdrE} ; + assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} : + MatchD ? {PredValidD, InstrClassD, PredPCD} : + {1'b1, InstrClassE, IEUAdrE} ; - flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); + flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF}; always_ff @ (posedge clk) begin if (reset) begin @@ -96,7 +96,7 @@ module btb #(parameter int Depth = 10 ) ( if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex]; end - assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; + //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; @@ -105,6 +105,6 @@ module btb #(parameter int Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); + flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD}); endmodule From 51a2a71410e5a069047f3bc2113c0f7e8dd0481d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 10:27:58 -0600 Subject: [PATCH 3/6] Removed unused signal. --- pipelined/src/ifu/bpred/bpred.sv | 2 +- pipelined/src/ifu/bpred/speculativegshare.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 9889607a4..c72e90148 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -116,7 +116,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, + .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 23a49eac3..1eb888a90 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -36,7 +36,7 @@ module speculativegshare #(parameter int k = 10 ) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE, input logic [3:0] WrongPredInstrClassD, input logic PCSrcE From 3276353b8c466c03f9f7aac8bf61a822f47801e8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 10:59:38 -0600 Subject: [PATCH 4/6] Minor branch predictor bug fix. --- pipelined/src/ifu/bpred/bpred.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index c72e90148..664149652 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -180,12 +180,14 @@ module bpred ( assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | PredInstrClassF[2] | - (PredInstrClassF[1]) ; + PredInstrClassF[1] | + PredInstrClassF[3]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) ; + (PredInstrClassF[1] & PredValidF) | + (PredInstrClassF[3] & PredValidF); end // Part 3 RAS From fc5692629a9213f0af243eadb6d7cbed667f7657 Mon Sep 17 00:00:00 2001 From: James Stine Date: Wed, 1 Feb 2023 17:03:48 -0600 Subject: [PATCH 5/6] Update ram2 and other memories and associated wrappers --- pipelined/src/generic/mem/ram2p1r1wbe.sv | 92 +++++++++--- ...1wbe_1024x69.sv => ram2p1r1wbe_1024x68.sv} | 18 +-- .../src/generic/mem/ram2p1r1wbe_64x32.sv | 48 ++++++ pipelined/src/generic/mem/rom1p1r.sv | 137 +++++++++--------- pipelined/src/generic/mem/rom1p1r_128x32.sv | 2 +- pipelined/src/generic/mem/rom1p1r_128x64.sv | 37 +++++ 6 files changed, 234 insertions(+), 100 deletions(-) rename pipelined/src/generic/mem/{ram2p1r1wbe_1024x69.sv => ram2p1r1wbe_1024x68.sv} (83%) create mode 100755 pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv create mode 100755 pipelined/src/generic/mem/rom1p1r_128x64.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe.sv b/pipelined/src/generic/mem/ram2p1r1wbe.sv index 49354075b..3c93ce868 100644 --- a/pipelined/src/generic/mem/ram2p1r1wbe.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe.sv @@ -5,7 +5,9 @@ // Two port SRAM 1 read port and 1 write port. // When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. -// Write +// Write +// Modified: james.stine@okstate.edu Feb 1, 2023 +// Integration of memories // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // @@ -42,31 +44,79 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( output logic [WIDTH-1:0] rd1 ); - logic [WIDTH-1:0] mem[DEPTH-1:0]; + logic [WIDTH-1:0] mem[DEPTH-1:0]; + localparam SRAMWIDTH = 32; + localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; // *************************************************************************** // TRUE Smem macro // *************************************************************************** - // *************************************************************************** - // READ first SRAM model - // *************************************************************************** - integer i; + if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin + + ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); - // Read - always_ff @(posedge clk) - if(ce1) rd1 <= #1 mem[ra1]; - - // Write divided into part for bytes and part for extra msbs - if(WIDTH >= 8) - always @(posedge clk) - if (ce2 & we2) - for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; - - if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always @(posedge clk) - if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; + end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin + logic [SRAMWIDTH-1:0] SRAMReadData; + logic [SRAMWIDTH-1:0] SRAMWriteData; + logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; + logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; + logic [SRAMWIDTH-1:0] SRAMBitMask; + logic [$clog2(DEPTH)-1:0] RA1Q; + + + onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); + genvar index; + for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux + assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; + assign SRAMWriteData[index*2+1:index*2] = wd2; + assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; + end + flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); + assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; + ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .DA('0), + .DB(SRAMWriteData), + .BWEBA('0), .BWEBB(SRAMBitMask), + .QA(SRAMReadData), + .QB()); + + end else begin + + // *************************************************************************** + // READ first SRAM model + // *************************************************************************** + integer i; + + // Read + always_ff @(posedge clk) + if(ce1) rd1 <= #1 mem[ra1]; + + // Write divided into part for bytes and part for extra msbs + if(WIDTH >= 8) + always @(posedge clk) + if (ce2 & we2) + for(i = 0; i < WIDTH/8; i++) + if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; + + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 + always @(posedge clk) + if (ce2 & we2 & bwe2[WIDTH/8]) + mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; + + end + endmodule diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv similarity index 83% rename from pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv rename to pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv index 4437c09bf..11eacd5ae 100755 --- a/pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// ram2p1rwbe_1024x69.sv +// ram2p1rwbe_1024x68.sv // // Written: james.stine@okstate.edu 28 January 2023 // Modified: @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ram2p1r1wbe_1024x69( +module ram2p1r1wbe_1024x68( input logic CLKA, input logic CLKB, input logic CEBA, @@ -33,16 +33,16 @@ module ram2p1r1wbe_1024x69( input logic WEBB, input logic [9:0] AA, input logic [9:0] AB, - input logic [68:0] DA, - input logic [68:0] DB, - input logic [68:0] BWEBA, - input logic [68:0] BWEBB, - output logic [68:0] QA, - output logic [68:0] QB + input logic [67:0] DA, + input logic [67:0] DB, + input logic [67:0] BWEBA, + input logic [67:0] BWEBB, + output logic [67:0] QA, + output logic [67:0] QB ); // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor - generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv b/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv new file mode 100755 index 000000000..8bc19637d --- /dev/null +++ b/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// ram2p1rwbe_64x32.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram2p1r1wbe_64x32( + input logic CLKA, + input logic CLKB, + input logic CEBA, + input logic CEBB, + input logic WEBA, + input logic WEBB, + input logic [5:0] AA, + input logic [5:0] AB, + input logic [31:0] DA, + input logic [31:0] DB, + input logic [31:0] BWEBA, + input logic [31:0] BWEBB, + output logic [31:0] QA, + output logic [31:0] QB +); + + // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor + generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + +endmodule diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 90bb87f9e..4669cadb8 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -27,74 +27,73 @@ `include "wally-config.vh" -module rom1p1r - #( - //-------------------------------------------------------------------------- - parameter ADDR_WIDTH = 8, - // Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth - parameter DATA_WIDTH = 32, // Data Width in bits - parameter PRELOAD_ENABLED = 0 - //---------------------------------------------------------------------- - ) ( - input logic clk, - input logic ce, - input logic [ADDR_WIDTH-1:0] addr, - output logic [DATA_WIDTH-1:0] dout - ); - // Core Memory - logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; +module rom1p1r #(parameter ADDR_WIDTH = 8, + parameter DATA_WIDTH = 32, + parameter PRELOAD_ENABLED = 0) + (input logic clk, + input logic ce, + input logic [ADDR_WIDTH-1:0] addr, + output logic [DATA_WIDTH-1:0] dout +); - always @ (posedge clk) begin - if(ce) dout <= ROM[addr]; - end + // Core Memory + logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; + if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin + rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); - // for FPGA, initialize with zero-stage bootloader - if(PRELOAD_ENABLED) begin - initial begin - ROM[0] = 64'h9581819300002197; - ROM[1] = 64'h4281420141014081; - ROM[2] = 64'h4481440143814301; - ROM[3] = 64'h4681460145814501; - ROM[4] = 64'h4881480147814701; - ROM[5] = 64'h4a814a0149814901; - ROM[6] = 64'h4c814c014b814b01; - ROM[7] = 64'h4e814e014d814d01; - ROM[8] = 64'h0110011b4f814f01; - ROM[9] = 64'h059b45011161016e; - ROM[10] = 64'h0004063705fe0010; - ROM[11] = 64'h05a000ef8006061b; - ROM[12] = 64'h0ff003930000100f; - ROM[13] = 64'h4e952e3110060e37; - ROM[14] = 64'hc602829b0053f2b7; - ROM[15] = 64'h2023fe02dfe312fd; - ROM[16] = 64'h829b0053f2b7007e; - ROM[17] = 64'hfe02dfe312fdc602; - ROM[18] = 64'h4de31efd000e2023; - ROM[19] = 64'h059bf1402573fdd0; - ROM[20] = 64'h0000061705e20870; - ROM[21] = 64'h0010029b01260613; - ROM[22] = 64'h11010002806702fe; - ROM[23] = 64'h84b2842ae426e822; - ROM[24] = 64'h892ee04aec064511; - ROM[25] = 64'h06e000ef07e000ef; - ROM[26] = 64'h979334fd02905563; - ROM[27] = 64'h07930177d4930204; - ROM[28] = 64'h4089093394be2004; - ROM[29] = 64'h04138522008905b3; - ROM[30] = 64'h19e3014000ef2004; - ROM[31] = 64'h64a2644260e2fe94; - ROM[32] = 64'h6749808261056902; - ROM[33] = 64'hdfed8b8510472783; - ROM[34] = 64'h2423479110a73823; - ROM[35] = 64'h10472783674910f7; - ROM[36] = 64'h20058693ffed8b89; - ROM[37] = 64'h05a1118737836749; - ROM[38] = 64'hfed59be3fef5bc23; - ROM[39] = 64'h1047278367498082; - ROM[40] = 64'h47858082dfed8b85; - ROM[41] = 64'h40a7853b4015551b; - ROM[42] = 64'h808210a7a02367c9; - end -end - -endmodule // bytewrite_tdp_ram_rf + end else begin + always @ (posedge clk) begin + if(ce) dout <= ROM[addr]; + end + + // for FPGA, initialize with zero-stage bootloader + if(PRELOAD_ENABLED) begin + initial begin + ROM[0] = 64'h9581819300002197; + ROM[1] = 64'h4281420141014081; + ROM[2] = 64'h4481440143814301; + ROM[3] = 64'h4681460145814501; + ROM[4] = 64'h4881480147814701; + ROM[5] = 64'h4a814a0149814901; + ROM[6] = 64'h4c814c014b814b01; + ROM[7] = 64'h4e814e014d814d01; + ROM[8] = 64'h0110011b4f814f01; + ROM[9] = 64'h059b45011161016e; + ROM[10] = 64'h0004063705fe0010; + ROM[11] = 64'h05a000ef8006061b; + ROM[12] = 64'h0ff003930000100f; + ROM[13] = 64'h4e952e3110060e37; + ROM[14] = 64'hc602829b0053f2b7; + ROM[15] = 64'h2023fe02dfe312fd; + ROM[16] = 64'h829b0053f2b7007e; + ROM[17] = 64'hfe02dfe312fdc602; + ROM[18] = 64'h4de31efd000e2023; + ROM[19] = 64'h059bf1402573fdd0; + ROM[20] = 64'h0000061705e20870; + ROM[21] = 64'h0010029b01260613; + ROM[22] = 64'h11010002806702fe; + ROM[23] = 64'h84b2842ae426e822; + ROM[24] = 64'h892ee04aec064511; + ROM[25] = 64'h06e000ef07e000ef; + ROM[26] = 64'h979334fd02905563; + ROM[27] = 64'h07930177d4930204; + ROM[28] = 64'h4089093394be2004; + ROM[29] = 64'h04138522008905b3; + ROM[30] = 64'h19e3014000ef2004; + ROM[31] = 64'h64a2644260e2fe94; + ROM[32] = 64'h6749808261056902; + ROM[33] = 64'hdfed8b8510472783; + ROM[34] = 64'h2423479110a73823; + ROM[35] = 64'h10472783674910f7; + ROM[36] = 64'h20058693ffed8b89; + ROM[37] = 64'h05a1118737836749; + ROM[38] = 64'hfed59be3fef5bc23; + ROM[39] = 64'h1047278367498082; + ROM[40] = 64'h47858082dfed8b85; + ROM[41] = 64'h40a7853b4015551b; + ROM[42] = 64'h808210a7a02367c9; + end + end + end + +endmodule diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/pipelined/src/generic/mem/rom1p1r_128x32.sv index 89d46b8f1..bc16a76dc 100755 --- a/pipelined/src/generic/mem/rom1p1r_128x32.sv +++ b/pipelined/src/generic/mem/rom1p1r_128x32.sv @@ -4,7 +4,7 @@ // Written: james.stine@okstate.edu 28 January 2023 // Modified: // -// Purpose: RAM wrapper for instantiating RAM IP +// Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/pipelined/src/generic/mem/rom1p1r_128x64.sv b/pipelined/src/generic/mem/rom1p1r_128x64.sv new file mode 100755 index 000000000..14e83f5f5 --- /dev/null +++ b/pipelined/src/generic/mem/rom1p1r_128x64.sv @@ -0,0 +1,37 @@ +/////////////////////////////////////////// +// rom1p1r_128x64.sv +// +// Written: james.stine@okstate.edu 28 January 2023 +// Modified: +// +// Purpose: ROM wrapper for instantiating ROM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rom1p1r_128x64( + input logic CLK, + input logic CEB, + input logic [6:0] A, + output logic [63:0] Q +); + + // replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor + generic64x128ROM romIP (.CLK, .CEB, .A, .Q); + +endmodule From 3838ab232bd663e883e06fb73c253a4141741c8f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 2 Feb 2023 08:52:06 -0600 Subject: [PATCH 6/6] Fixed bug #47 discovered by Lee Moore. ECALL and EBREAK do not commit their results. --- pipelined/src/hazard/hazard.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 9dd3c0e4b..650e8367d 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -68,7 +68,7 @@ module hazard ( assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE; assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE)); assign FlushMCause = TrapM | RetM | CSRWriteFenceM; - assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM); + assign FlushWCause = TrapM; // Stall causes // Most data depenency stalls are identified in the decode stage