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Removed lsuArb and placed remaining logic in lsu.sv.

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Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
This commit is contained in:
Ross Thompson 2021-12-19 21:34:40 -06:00
parent 019e300a14
commit 30770db4ac
5 changed files with 167 additions and 286 deletions
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2
wally-pipelined/src/cache/dcache.sv vendored
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@ -53,7 +53,6 @@ module dcache
input logic CacheableM, input logic CacheableM,
// from ptw // from ptw
input logic IgnoreRequest, input logic IgnoreRequest,
output logic MemAfterIWalkDone,
// ahb side // ahb side
(* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb (* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
(* mark_debug = "true" *)output logic AHBRead, (* mark_debug = "true" *)output logic AHBRead,
@ -358,7 +357,6 @@ module dcache
.CommittedM, .CommittedM,
.DCacheMiss, .DCacheMiss,
.DCacheAccess, .DCacheAccess,
.MemAfterIWalkDone,
.AHBRead, .AHBRead,
.AHBWrite, .AHBWrite,
.SelAdrM, .SelAdrM,

3
wally-pipelined/src/cache/dcachefsm.sv vendored
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@ -53,8 +53,6 @@ module dcachefsm
// counter outputs // counter outputs
output logic DCacheMiss, output logic DCacheMiss,
output logic DCacheAccess, output logic DCacheAccess,
// hptw outputs
output logic MemAfterIWalkDone,
// Bus outputs // Bus outputs
output logic AHBRead, output logic AHBRead,
output logic AHBWrite, output logic AHBWrite,
@ -137,7 +135,6 @@ module dcachefsm
SelUncached = 1'b0; SelUncached = 1'b0;
SelEvict = 1'b0; SelEvict = 1'b0;
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
MemAfterIWalkDone = 1'b0;
SelFlush = 1'b0; SelFlush = 1'b0;
FlushAdrCntEn = 1'b0; FlushAdrCntEn = 1'b0;
FlushWayCntEn = 1'b0; FlushWayCntEn = 1'b0;

74
wally-pipelined/src/lsu/lsu.sv
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@ -93,7 +93,6 @@ module lsu
); );
logic DTLBPageFaultM; logic DTLBPageFaultM;
logic DataMisalignedM;
logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache
@ -111,8 +110,7 @@ module lsu
logic [11:0] MemAdrE, MemAdrE_RENAME; logic [11:0] MemAdrE, MemAdrE_RENAME;
logic StallWtoDCache; logic StallWtoDCache;
logic MemReadM; logic MemReadM;
logic DataMisalignedMfromDCache; logic DataMisalignedM;
logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB.
logic DCacheStall; logic DCacheStall;
logic CacheableM; logic CacheableM;
@ -272,9 +270,7 @@ module lsu
.DCacheStall(DCacheStall), .DCacheStall(DCacheStall),
.TranslationPAdr, .TranslationPAdr,
.HPTWRead(HPTWRead), .HPTWRead(HPTWRead),
.HPTWStall,
.AnyCPUReqM, .AnyCPUReqM,
.MemAfterIWalkDone,
.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw), .WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
.WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerLoadPageFaultM(WalkerLoadPageFaultM),
.WalkerStorePageFaultM(WalkerStorePageFaultM)); .WalkerStorePageFaultM(WalkerStorePageFaultM));
@ -284,37 +280,36 @@ module lsu
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM; assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
// arbiter between IEU and hptw // arbiter between IEU and hptw
lsuArb arbiter(.clk(clk), logic [2:0] PTWSize;
// HPTW connection logic [`PA_BITS-1:0] TranslationPAdrM;
.SelPTW, logic [`XLEN+1:0] IEUAdrMExt;
.HPTWRead(HPTWRead),
.TranslationPAdrE(TranslationPAdr), // multiplex the outputs to LSU
// CPU connection assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
.MemRWM(MemRWM),
.Funct3M(Funct3M), generate
.AtomicM(AtomicM), assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
.IEUAdrM(IEUAdrM), endgenerate
.IEUAdrE(IEUAdrE[11:0]), mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
.CommittedM(CommittedM),
.PendingInterruptM(PendingInterruptM), // this is for the d cache SRAM.
.StallW(StallW), flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM); // delay TranslationPAdrM by a cycle
.DataMisalignedM(DataMisalignedM),
// DCACHE assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
.DisableTranslation(DisableTranslation), assign IEUAdrMExt = {2'b00, IEUAdrM};
.MemRWMtoLRSC(MemRWMtoLRSC), assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0];
.Funct3MtoDCache(Funct3MtoDCache), assign MemAdrE = SelPTW ? TranslationPAdr[11:0] : IEUAdrE[11:0];
.AtomicMtoDCache(AtomicMtoDCache), assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
.MemPAdrNoTranslate(MemPAdrNoTranslate), // always block interrupts when using the hardware page table walker.
.MemAdrE(MemAdrE), assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
.StallWtoDCache(StallWtoDCache),
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
.CommittedMfromDCache(CommittedMfromDCache), assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
.DCacheStall(DCacheStall));
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation(DisableTranslation), .PrivilegeModeW, .DisableTranslation(SelPTW),
.PAdr(MemPAdrNoTranslate), .PAdr(MemPAdrNoTranslate),
.VAdr(IEUAdrM), .VAdr(IEUAdrM),
.Size(Funct3MtoDCache[1:0]), .Size(Funct3MtoDCache[1:0]),
@ -353,15 +348,15 @@ module lsu
// Determine if an Unaligned access is taking place // Determine if an Unaligned access is taking place
always_comb always_comb
case(Funct3MtoDCache[1:0]) case(Funct3MtoDCache[1:0])
2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu 2'b00: DataMisalignedM = 0; // lb, sb, lbu
2'b01: DataMisalignedMfromDCache = MemPAdrNoTranslate[0]; // lh, sh, lhu 2'b01: DataMisalignedM = MemPAdrNoTranslate[0]; // lh, sh, lhu
2'b10: DataMisalignedMfromDCache = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu 2'b10: DataMisalignedM = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu
2'b11: DataMisalignedMfromDCache = |MemPAdrNoTranslate[2:0]; // ld, sd, fld, fsd 2'b11: DataMisalignedM = |MemPAdrNoTranslate[2:0]; // ld, sd, fld, fsd
endcase endcase
// Determine if address is valid // Determine if address is valid
assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1]; assign LoadMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[1];
assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0]; assign StoreMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[0];
// conditional // conditional
// 1. ram // controlled by `MEM_DTIM // 1. ram // controlled by `MEM_DTIM
@ -390,7 +385,6 @@ module lsu
.IgnoreRequest, .IgnoreRequest,
.PendingInterruptM(PendingInterruptMtoDCache), .PendingInterruptM(PendingInterruptMtoDCache),
.CacheableM(CacheableMtoDCache), .CacheableM(CacheableMtoDCache),
.MemAfterIWalkDone,
// AHB connection // AHB connection
.AHBPAdr(DCtoAHBPAdrM), .AHBPAdr(DCtoAHBPAdrM),

105
wally-pipelined/src/lsu/lsuArb.sv
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@ -1,105 +0,0 @@
///////////////////////////////////////////
// lsuArb.sv
//
// Written: Ross THompson and Kip Macsai-Goren
// Modified: kmacsaigoren@hmc.edu June 23, 2021
//
// Purpose: LSU arbiter between the CPU's demand request for data memory and
// the page table walker
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module lsuArb
(input logic clk,
// from page table walker
input logic SelPTW,
input logic HPTWRead,
input logic [`PA_BITS-1:0] TranslationPAdrE,
// from CPU
input logic [1:0] MemRWM,
input logic [2:0] Funct3M,
input logic [1:0] AtomicM,
input logic [`XLEN-1:0] IEUAdrM,
input logic [11:0] IEUAdrE,
input logic StallW,
input logic PendingInterruptM,
// to CPU
output logic DataMisalignedM,
output logic CommittedM,
//output logic LSUStall,
// to D Cache
output logic DisableTranslation,
output logic [1:0] MemRWMtoLRSC,
output logic [2:0] Funct3MtoDCache,
output logic [1:0] AtomicMtoDCache,
output logic [`PA_BITS-1:0] MemPAdrNoTranslate, // THis name is very bad. need a better name. This is the raw address from either the ieu or the hptw.
output logic [11:0] MemAdrE,
output logic StallWtoDCache,
output logic PendingInterruptMtoDCache,
// from D Cache
input logic CommittedMfromDCache,
input logic DataMisalignedMfromDCache,
input logic DCacheStall
);
logic [2:0] PTWSize;
logic [`PA_BITS-1:0] TranslationPAdrM;
logic [`XLEN+1:0] IEUAdrMExt;
// multiplex the outputs to LSU
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
generate
assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
endgenerate
mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
// this is for the d cache SRAM.
flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM); // delay TranslationPAdrM by a cycle
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
assign IEUAdrMExt = {2'b00, IEUAdrM};
assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0];
assign MemAdrE = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
// always block interrupts when using the hardware page table walker.
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
// demux the inputs from LSU to walker or cpu's data port.
// works without the demux 7/18/21 dh. Suggest deleting these and removing fromDCache suffix
assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache;
// *** need to rename DcacheStall and Datastall.
// not clear at all. I think it should be LSUStall from the LSU,
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
//assign HPTWStall = SelPTW ? DCacheStall : 1'b1;
assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
//assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
endmodule

9
wally-pipelined/src/mmu/hptw.sv
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@ -39,7 +39,6 @@ module hptw
input logic [1:0] MemRWM, // 10 = read, 01 = write input logic [1:0] MemRWM, // 10 = read, 01 = write
input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
input logic DCacheStall, // stall from LSU input logic DCacheStall, // stall from LSU
input logic MemAfterIWalkDone,
input logic AnyCPUReqM, input logic AnyCPUReqM,
output logic [`XLEN-1:0] PTE, // page table entry to TLBs output logic [`XLEN-1:0] PTE, // page table entry to TLBs
output logic [1:0] PageType, // page type to TLBs output logic [1:0] PageType, // page type to TLBs
@ -54,7 +53,7 @@ module hptw
L1_ADR, L1_RD, L1_ADR, L1_RD,
L2_ADR, L2_RD, L2_ADR, L2_RD,
L3_ADR, L3_RD, L3_ADR, L3_RD,
LEAF, LEAF_DELAY, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
generate generate
if (`MEM_VIRTMEM) begin if (`MEM_VIRTMEM) begin
@ -198,10 +197,8 @@ module hptw
else NextWalkerState = LEAF; else NextWalkerState = LEAF;
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF; // LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
// else NextWalkerState = FAULT; // else NextWalkerState = FAULT;
LEAF: if (DTLBWalk) NextWalkerState = IDLE; // updates TLB LEAF: NextWalkerState = IDLE; // updates TLB
else NextWalkerState = IDLE; FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT;
LEAF_DELAY: NextWalkerState = IDLE; // give time to allow address translation
FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
default: begin default: begin
// synthesis translate_off // synthesis translate_off