From 30694f4ed0a64af46061884a03d3b9afdd67bdf5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 25 Aug 2024 14:46:22 -0700 Subject: [PATCH] Fixed imperas configuration and updated files for new Imperas/Synopsys licenses --- bin/regression-wally | 3 ++- sim/imperas.ic | 2 +- site-setup.sh | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index cd4844b08..1c3cde58e 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -371,6 +371,7 @@ args = parser.parse_args() if (args.nightly): nightMode = "--nightly"; sims = ["questa", "verilator", "vcs"] # exercise all simulators; can omit a sim if no license is available +# sims = ["questa", "verilator"] # exercise all simulators; can omit a sim if no license is available else: nightMode = "" sims = [defaultsim] @@ -512,7 +513,7 @@ def main(): elif args.fcov: TIMEOUT_DUR = 1*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') - elif args.nightly: + elif args.buildroot: TIMEOUT_DUR = 60*1440 # 1 day elif args.testfloat: TIMEOUT_DUR = 30*60 # seconds diff --git a/sim/imperas.ic b/sim/imperas.ic index aee25eabf..b3485aff7 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -74,7 +74,7 @@ --override cpu/PMP_undefined=T # mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception ---override cpu/mstatus_fs_mode=rvfs_write_nz +--override cpu/mstatus_fs_mode=write_1 # PMA Settings # 'r': read access allowed diff --git a/site-setup.sh b/site-setup.sh index e2affd031..de10a758e 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -11,6 +11,7 @@ # Must edit these based on your local environment. export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server +export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Imperas license server export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin