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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally

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Katherine Parry 2022-07-15 20:17:08 +00:00
commit 304c81eb17
3 changed files with 9 additions and 9 deletions
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4
pipelined/srt/sqrttestgen.c
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@ -32,9 +32,9 @@ void main(void)
int aExp, rExp; int aExp, rExp;
double mans[ENTRIES] = {1, 1849.0/1024, 1.25, 1.125, 1.0625, double mans[ENTRIES] = {1, 1849.0/1024, 1.25, 1.125, 1.0625,
1.75, 1.875, 1.99999, 1.75, 1.875, 1.99999,
1.1, 1.2, 1.01, 1.001, 1.0001, 1.1, 1.5, 1.01, 1.001, 1.0001,
2/1.1, 2/1.5, 2/1.25, 2/1.125}; 2/1.1, 2/1.5, 2/1.25, 2/1.125};
double exps[ENTRIES] = {0, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, double exps[ENTRIES] = {0, 0, 2, 3, 4, 5, 6, 7, 8, 1, 10,
11, 12, 13, 14, 15, 16}; 11, 12, 13, 14, 15, 16};
int i; int i;
int bias = 1023; int bias = 1023;

11
pipelined/srt/srt.sv
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@ -75,7 +75,7 @@ module srt (
// Quotient Selection logic // Quotient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], qp, qz, qn); qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN-1], WC[`DIVLEN+3:`DIVLEN-1], Sqrt, qp, qz, qn);
flopen #(`NE) expflop(clk, Start, calcExp, rExp); flopen #(`NE) expflop(clk, Start, calcExp, rExp);
flopen #(1) signflop(clk, Start, calcSign, rsign); flopen #(1) signflop(clk, Start, calcSign, rsign);
@ -169,11 +169,12 @@ endmodule
// Quotient Selection, Radix 2 // // Quotient Selection, Radix 2 //
///////////////////////////////// /////////////////////////////////
module qsel2 ( // *** eventually just change to 4 bits module qsel2 ( // *** eventually just change to 4 bits
input logic [`DIVLEN+3:`DIVLEN] ps, pc, input logic [`DIVLEN+3:`DIVLEN-1] ps, pc,
input logic Sqrt,
output logic qp, qz, qn output logic qp, qz, qn
); );
logic [`DIVLEN+3:`DIVLEN] p, g; logic [`DIVLEN+3:`DIVLEN-1] p, g;
logic magnitude, sign, cout; logic magnitude, sign, cout;
// The quotient selection logic is presented for simplicity, not // The quotient selection logic is presented for simplicity, not
@ -184,8 +185,8 @@ module qsel2 ( // *** eventually just change to 4 bits
assign p = ps ^ pc; assign p = ps ^ pc;
assign g = ps & pc; assign g = ps & pc;
assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN]); assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN-1]);
assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & g[`DIVLEN])); assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & (g[`DIVLEN] | (Sqrt & (p[`DIVLEN] & g[`DIVLEN-1])))));
assign #1 sign = p[`DIVLEN+3] ^ cout; assign #1 sign = p[`DIVLEN+3] ^ cout;
/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) & /* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
(ps[52]^pc[52])); (ps[52]^pc[52]));

3
pipelined/srt/testbench.sv
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@ -160,10 +160,9 @@ module testbench;
errors = errors + 1; errors = errors + 1;
$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
$display("failed\n"); $display("failed\n");
$stop;
end end
if (afrac === 52'hxxxxxxxxxxxxx) begin if (afrac === 52'hxxxxxxxxxxxxx) begin
$display("%d Tests completed successfully", testnum); $display("%d Tests completed successfully", testnum-errors);
$stop; end $stop; end
end end
end end