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https://github.com/openhwgroup/cvw
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Added tcl commands to build the implementation.
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@ -74,3 +74,28 @@ report_timing -nworst 1 -delay_type max -sort_by group -file re
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report_utilization -hierarchical -file reports/utilization.rpt
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report_utilization -hierarchical -file reports/utilization.rpt
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report_cdc -file reports/cdc.rpt
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report_cdc -file reports/cdc.rpt
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report_clock_interaction -file reports/clock_interaction.rpt
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report_clock_interaction -file reports/clock_interaction.rpt
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# set for RuntimeOptimized implementation
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#set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
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#set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
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launch_runs impl_1
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wait_on_run impl_1
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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open_run impl_1
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# output Verilog netlist + SDC for timing simulation
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exec mkdir -p sim/
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exec rm -rf sim/*
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write_verilog -force -mode funcsim sim/funcsim.v
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write_verilog -force -mode timesim sim/timesim.v
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write_sdf -force sim/timesim.sdf
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# reports
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check_timing -file reports/imp_check_timing.rpt
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report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack -file reports/imp_timing_WORST_10.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/imp_timing.rpt
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report_utilization -hierarchical -file reports/imp_utilization.rpt
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