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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-04-01 12:50:34 -05:00
commit 301f20052b
8 changed files with 281 additions and 48 deletions
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20
fpga/constraints/debug2.xdc
View File

@ -631,3 +631,23 @@ create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe133] set_property port_width 64 [get_debug_ports u_ila_0/probe133]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]] connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe134]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134]
connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11]} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe135]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135]
connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore/plic.plic/requests[12]}]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe136]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136]
connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[12]}]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe137]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]]

4
linux/buildroot-scripts/Makefile
View File

@ -19,10 +19,10 @@ disassemble:
# -cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio # -cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio
${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf ${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf
riscv64-unknown-elf-objdump -D ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump riscv64-unknown-elf-objdump -S ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump
${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux ${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux
riscv64-unknown-elf-objdump -D ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump riscv64-unknown-elf-objdump -S ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump
${DIS}/vmlinux.objdump.addr: ${DIS}/vmlinux.objdump ${DIS}/vmlinux.objdump.addr: ${DIS}/vmlinux.objdump
-cd ${DIS}; extractFunctionRadix.sh vmlinux.objdump -cd ${DIS}; extractFunctionRadix.sh vmlinux.objdump

50
pipelined/regression/wave.do
View File

@ -27,7 +27,6 @@ add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
@ -92,7 +91,7 @@ add wave -noupdate -group Bpred -group {branch update selection inputs} /testben
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
@ -214,7 +213,6 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
@ -383,7 +381,6 @@ add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress
@ -391,11 +388,11 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/pl
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingArray
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingMaxP
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingPGrouped
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingRequestsAtMaxP
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqMatrix
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/priorities_with_irqs
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/max_priority_with_irqs
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqs_at_max_priority
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
@ -425,21 +422,21 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LSR add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uart/uart/u/LSR
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MCR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MCR
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MSR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MSR
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/RBR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/RBR
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/TXHR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/TXHR
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LCR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/LCR
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate
@ -448,6 +445,11 @@ add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxoverrunerr
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataready
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataavailintr
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/RXBR
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/squashRXerrIP
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync
@ -526,4 +528,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ns} {496 ns} WaveRestoreZoom {0 ns} {208 ns}

49
pipelined/src/generic/flop/bram2p1r1w.sv
View File

@ -71,10 +71,59 @@ module bram2p1r1w
logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0]; logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0];
integer i; integer i;
/* -----\/----- EXCLUDED -----\/-----
initial begin initial begin
if(PRELOAD_ENABLED) if(PRELOAD_ENABLED)
$readmemh(PRELOAD_FILE, RAM); $readmemh(PRELOAD_FILE, RAM);
end end
-----/\----- EXCLUDED -----/\----- */
initial begin
if(PRELOAD_ENABLED) begin
RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301;
RAM[3] = 64'h4681460145814501;
RAM[4] = 64'h4881480147814701;
RAM[5] = 64'h4a814a0149814901;
RAM[6] = 64'h4c814c014b814b01;
RAM[7] = 64'h4e814e014d814d01;
RAM[8] = 64'h0110011b4f814f01;
RAM[9] = 64'h059b45011161016e;
RAM[10] = 64'h0004063705fe0010;
RAM[11] = 64'h05a000ef8006061b;
RAM[12] = 64'h0ff003930000100f;
RAM[13] = 64'h4e952e3110060e37;
RAM[14] = 64'hc602829b0053f2b7;
RAM[15] = 64'h2023fe02dfe312fd;
RAM[16] = 64'h829b0053f2b7007e;
RAM[17] = 64'hfe02dfe312fdc602;
RAM[18] = 64'h4de31efd000e2023;
RAM[19] = 64'h059bf1402573fdd0;
RAM[20] = 64'h0000061705e20870;
RAM[21] = 64'h0010029b01260613;
RAM[22] = 64'h11010002806702fe;
RAM[23] = 64'h84b2842ae426e822;
RAM[24] = 64'h892ee04aec064505;
RAM[25] = 64'h06e000ef07e000ef;
RAM[26] = 64'h979334fd02905563;
RAM[27] = 64'h07930177d4930204;
RAM[28] = 64'h4089093394be2004;
RAM[29] = 64'h04138522008905b3;
RAM[30] = 64'h19e3014000ef2004;
RAM[31] = 64'h64a2644260e2fe94;
RAM[32] = 64'h6749808261056902;
RAM[33] = 64'hdfed8b8510472783;
RAM[34] = 64'h2423479110a73823;
RAM[35] = 64'h10472783674910f7;
RAM[36] = 64'h20058693ffed8b89;
RAM[37] = 64'h05a1118737836749;
RAM[38] = 64'hfed59be3fef5bc23;
RAM[39] = 64'h1047278367498082;
RAM[40] = 64'h67c98082dfed8b85;
RAM[41] = 64'h0000808210a7a023;
end
end
// Port-A Operation // Port-A Operation
always @ (posedge clk) begin always @ (posedge clk) begin

8
pipelined/src/uncore/plic.sv
View File

@ -57,16 +57,16 @@ module plic (
input logic UARTIntr,GPIOIntr, input logic UARTIntr,GPIOIntr,
output logic [`XLEN-1:0] HREADPLIC, output logic [`XLEN-1:0] HREADPLIC,
output logic HRESPPLIC, HREADYPLIC, output logic HRESPPLIC, HREADYPLIC,
output logic MExtIntM, SExtIntM); (* mark_debug = "true" *) output logic MExtIntM, SExtIntM);
logic memwrite, memread, initTrans; logic memwrite, memread, initTrans;
logic [23:0] entry, entryd; logic [23:0] entry, entryd;
logic [31:0] Din, Dout; logic [31:0] Din, Dout;
// context-independent signals // context-independent signals
logic [`N:1] requests; (* mark_debug = "true" *) logic [`N:1] requests;
logic [`N:1][2:0] intPriority; (* mark_debug = "true" *) logic [`N:1][2:0] intPriority;
logic [`N:1] intInProgress, intPending, nextIntPending; (* mark_debug = "true" *) logic [`N:1] intInProgress, intPending, nextIntPending;
// context-dependent signals // context-dependent signals
logic [`C-1:0][2:0] intThreshold; logic [`C-1:0][2:0] intThreshold;

5
pipelined/src/uncore/uartPC16550D.sv
View File

@ -308,7 +308,10 @@ module uartPC16550D(
if (fifoenabled) begin if (fifoenabled) begin
if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1; if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1;
if (rxfifohead == rxfifotail +1) rxdataready <= #1 0; if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
end else rxdataready <= #1 0; end else begin
rxdataready <= #1 0;
RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
end
end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register
if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents
rxfifohead <= #1 0; rxfifotail <= #1 0; rxfifohead <= #1 0; rxfifotail <= #1 0;

64
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output
View File

@ -430,3 +430,67 @@ FFFFFF33
00000000 00000000
00000000 00000000
00000000 00000000
04BEEF1B
00000009
80000000
0000000A
00000004
00000061
00000061
00000065
00000060
00000001
00000000
00000000
00000000
00000000
00000000
00000000
04BEEF1C
00000009
80000000
00000003
00080000
00080000
00080000
00000000
00000000
00000000
00080000
00080000
FFFFFFFF
FFF7FFFF
00000000
00000000
04BEEF1D
00000009
80000000
00000003
00000001
00000001
00000001
00000000
00080000
00000000
00080001
00000001
FFFFFFFF
FFFFFFFE
00000000
00000000
04BEEF1E
00000009
80000000
0000000A
00000004
00000061
00000061
0000006e
00000060
00000001
00000000
00000000
00000000
00000000
00000000
00000000

129
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S
View File

@ -41,11 +41,12 @@ trap_handler: #####
################### ###################
################### ###################
# save registers # save registers
addi sp, sp, 0x20 addi sp, sp, 0x28
sw t0, 0x00(sp) sw t0, 0x00(sp)
sw t1, 0x08(sp) sw t1, 0x08(sp)
sw t2, 0x10(sp) sw t2, 0x10(sp)
sw t3, 0x18(sp) sw t3, 0x18(sp)
sw t4, 0x20(sp)
# =================================== # ===================================
# ===== Signature Output Format ===== # ===== Signature Output Format =====
@ -56,7 +57,7 @@ trap_handler: #####
# #
# <offset>: <contents> # <offset>: <contents>
# 0x00: test ID = 0x<group_num>BEEF<intr_num> # 0x00: test ID = 0x<group_num>BEEF<intr_num>
# 0x04: mcause (low) = 0x0000000B # 0x04: mcause (low) = 0x0000000B (MEIP) or 0x00000009 (SEIP)
# 0x08: mcause (high) = 0x80000000 # 0x08: mcause (high) = 0x80000000
# ----- If GPIO ----- # ----- If GPIO -----
# 0x0C: claim ID = 3 # 0x0C: claim ID = 3
@ -87,18 +88,26 @@ trap_handler: #####
add t0, t0, a1 add t0, t0, a1
sw t0, 0x00(s0) sw t0, 0x00(s0)
# 0x04: mcause (low) = 0x0000000B # 0x04: mcause (low) = 0x0000000B (MEIP) or 0x00000009 (SEIP)
# 0x08: mcause (high) = 0x80000000 # 0x08: mcause (high) = 0x80000000
# Expect interrupt from src 11 (machine external interrupt) csrrc t0, mcause, x0
csrrc t1, mcause, x0 andi t1, t0, 0x7FF
sw t1, 0x04(s0) sw t0, 0x04(s0)
srli t1,t1,32 srli t0,t0,32
sw t1, 0x08(s0) sw t0, 0x08(s0)
# MEIP or SEIP?
# MEIP is on context 0
li t4, 0x0C200004
li t0, 0xB
beq t1, t0, meip
# SEIP is on context 1
li t4, 0x0C201004
meip:
# 0x: claim ID # 0x0C: claim ID
# 3: GPIO # 3: GPIO
# A: UART # A: UART
li t0, 0x0C200004 mv t0, t4
lw t1, 0(t0) lw t1, 0(t0)
sw t1, 0x0C(s0) sw t1, 0x0C(s0)
li t2, 0xA li t2, 0xA
@ -150,7 +159,7 @@ trap_handler: #####
# signal to main code that gpio was serviced # signal to main code that gpio was serviced
ori a0, a0, 0b00001000 ori a0, a0, 0b00001000
# signal to plic that gpio was serviced # signal to plic that gpio was serviced
li t0, 0x0C200004 mv t0, t4
li t1, 3 li t1, 3
sw t1, 0(t0) sw t1, 0(t0)
j trap_handler_end j trap_handler_end
@ -181,7 +190,7 @@ trap_handler: #####
# signal to main code that uart was serviced # signal to main code that uart was serviced
ori a0, a0, 0b00010000 ori a0, a0, 0b00010000
# signal to plic that uart was serviced # signal to plic that uart was serviced
li t0, 0x0C200004 mv t0, t4
li t1, 0xA li t1, 0xA
sw t1, 0(t0) sw t1, 0(t0)
@ -193,7 +202,8 @@ trap_handler: #####
ld t1, 0x08(sp) ld t1, 0x08(sp)
ld t2, 0x10(sp) ld t2, 0x10(sp)
ld t3, 0x18(sp) ld t3, 0x18(sp)
addi sp, sp, SEXT_IMM(-0x20) ld t4, 0x20(sp)
addi sp, sp, SEXT_IMM(-0x28)
mret mret
################ ################
@ -267,7 +277,7 @@ main_code: #####
# set MEIE # set MEIE
li t0, 0x800 li t0, 0x800
csrrs x0, mie, t0 csrrs x0, mie, t0
Intr01BEEF01: Intr01BEEF00:
# UART TX 'h' # UART TX 'h'
li t0, 0x10000000 li t0, 0x10000000
li t1, 'h' li t1, 'h'
@ -276,7 +286,7 @@ Intr01BEEF01:
li t1, 0b00010000 li t1, 0b00010000
1: bne t1,a0,1b 1: bne t1,a0,1b
li a0, 0 li a0, 0
Intr01BEEF02: Intr01BEEF01:
# GPIO raise pin 19 # GPIO raise pin 19
li t0, 0x10060000 li t0, 0x10060000
li t1, 0x00080000 li t1, 0x00080000
@ -286,12 +296,12 @@ Intr01BEEF02:
1: bne t1,a0,1b 1: bne t1,a0,1b
li a0, 0 li a0, 0
# Now let's go bonkers and trigger both! # Now let's go bonkers and trigger both!
Intr01BEEF03: Intr01BEEF02:
# TX 'e' # TX 'e'
li t0, 0x10000000 li t0, 0x10000000
li t1, 'e' li t1, 'e'
sb t1, 0(t0) sb t1, 0(t0)
Intr01BEEF04: Intr01BEEF03:
# GPIO lower pin 19 raise pin 0 # GPIO lower pin 19 raise pin 0
li t0, 0x10060000 li t0, 0x10060000
li t1, 0x00000001 li t1, 0x00000001
@ -787,6 +797,91 @@ Intr03BEEF1A:
li t1, 0b00010000 li t1, 0b00010000
1: bne t1,a0,1b 1: bne t1,a0,1b
li a0, 0 li a0, 0
####################################################
##### Test 4 - Signs of Life on PLIC Context 1 #####
####################################################
li a1, 0x04beef00 # group ID
# clear MEIE (good to turn off while configuring peripherals)
li t0, 0x800
csrrc x0, mie, t0
# ========== Configure PLIC ==========
# priority threshold = 0
li t0, 0xC200000
li t1, 0
sw t1, 0(t0)
# source 3 (GPIO) priority = 6
li t0, 0xC000000
li t1, 6
sw t1, 0x0C(t0)
# source 0xA (UART) priority = 7
li t1, 7
sw t1, 0x28(t0)
# disable sources 3,0xA on context 0
li t0, 0x0C002000
li t1, 0
sw t1, 0(t0)
# enable sources 3,0xA on context 1
li t0, 0x0C002080
li t1, 0b10000001000
sw t1, 0(t0)
# ========== Configure UART ==========
# MCR: Loop = 1
li t0, 0x10000000
li t1, 0b10000
sb t1, 4(t0)
# LCR: Use 8 data bits plus odd parity bit
li t1, 0b00001011
sb t1, 3(t0)
# IER: Enable Received Data Available Interrupt
li t1, 0x01
sb t1, 1(t0)
# ========== Configure GPIO ==========
# raise all input_en
li t0, 0x10060000
li t1, 0xFFFFFFFF
sw t1, 0x04(t0)
# raise all output_en
sw t1, 0x08(t0)
# raise all input_en
sw t1, 0x18(t0)
# ========== Execute Test ==========
# set MEIE and SEIE
li t0, 0xA00
csrrs x0, mie, t0
Intr04BEEF1B:
# UART TX 'e'
li t0, 0x10000000
li t1, 'e'
sb t1, 0(t0)
# wait to finish
li t1, 0b00010000
1: bne t1,a0,1b
li a0, 0
Intr04BEEF1C:
# GPIO raise pin 19
li t0, 0x10060000
li t1, 0x00080000
sw t1, 0x0C(t0)
# wait to finish
li t1, 0b00001000
1: bne t1,a0,1b
li a0, 0
# Now let's go bonkers and trigger both!
Intr04BEEF1D:
# TX 'n'
li t0, 0x10000000
li t1, 'n'
sb t1, 0(t0)
Intr04BEEF1E:
# GPIO lower pin 19 raise pin 0
li t0, 0x10060000
li t1, 0x00000001
sw t1, 0x0C(t0)
# wait to finish
li t1, 0b00011000
1: bne t1,a0,1b
li a0, 0
# --------------------------------------------------------------------------------------------- # ---------------------------------------------------------------------------------------------
//terminate_test: //terminate_test: