diff --git a/bin/regression-wally b/bin/regression-wally
index 9291faabc..1d0a79c39 100755
--- a/bin/regression-wally
+++ b/bin/regression-wally
@@ -320,7 +320,7 @@ def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0, breke
     # fcov/ccov only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
     fileEnd = "ALL.elf" if "cvw-arch-verif/tests" in testDir and "priv" not in testDir and (coverStr == "--fcov" or coverStr == "--ccov") else ".elf"
     if lockstepMode or coverStr == "--fcov":
-        gs = "Mismatches            : 0"
+        gs = "** Note: $finish"
     elif brekerMode:
         gs="# trek: info: summary: Test PASSED"
     else:
diff --git a/bin/wsim b/bin/wsim
index c8ec316fe..c8592d993 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -101,13 +101,11 @@ def prepSim(args, ElfFile):
         flagsList.append("--ccov")
     if args.fcov:
         flagsList.append("--fcov")
-        defineList.extend(["+define+ENABLE_RVVI_TRACE", "+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests
-        argsList.extend(["+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1"])
+        defineList.extend(["+define+ENABLE_RVVI_TRACE", "+define+FCOV"])
     if args.gui:
         flagsList.append("--gui")
     if args.lockstep or args.lockstepverbose:
         flagsList.append("--lockstep")
-    if args.lockstep or args.lockstepverbose:
         prefix = lockstepSetup(args)
         defineList.extend(["+define+USE_IMPERAS_DV", "+define+ENABLE_RVVI_TRACE"])
     if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details
diff --git a/sim/imperas-verbose.ic b/sim/imperas-verbose.ic
index fca9e072c..7cd53e38e 100644
--- a/sim/imperas-verbose.ic
+++ b/sim/imperas-verbose.ic
@@ -1,4 +1,3 @@
 # Add Imperas simulator application instruction tracing
---verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000
+--verbose --trace --tracechange --traceshowicount --tracemode --tracemem XSL --monitornetschange # --traceafter 300000000
 --override cpu/debugflags=6 --override cpu/verbose=1
---override cpu/show_c_prefix=T
diff --git a/sim/questa/wally.do b/sim/questa/wally.do
index 22c0c8e68..ba9891c0d 100644
--- a/sim/questa/wally.do
+++ b/sim/questa/wally.do
@@ -113,16 +113,11 @@ if {[lcheck lst "--ccov"]} {
 if {[lcheck lst "--fcov"]} {
     set IMPERAS_HOME $::env(IMPERAS_HOME)
     set FunctCoverage 1
-    # ImpProprietary is needed for trace2cov for now
     set FCvlog "+incdir+${FCRVVI}/unpriv \
                 +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \
                 +incdir+${FCRVVI}/common +incdir+${FCRVVI} \
                 +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \
-                +incdir+${IMPERAS_HOME}/ImpPublic/include/host \
-                +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \
-                ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \
-                ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv"
-    set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model "
+                ${FCRVVI}/*.sv"
 }
 
 # if --lockstep found set flag and remove from list
diff --git a/testbench/common/trace2riscvISACOV.sv b/testbench/common/trace2riscvISACOV.sv
new file mode 100644
index 000000000..0f8d3f612
--- /dev/null
+++ b/testbench/common/trace2riscvISACOV.sv
@@ -0,0 +1,25 @@
+// trace2riscvISACOV.sv
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+`include "RISCV_coverage.svh"
+
+module trace2riscvISACOV(rvviTrace rvvi);
+  // Connect coverage class to RVVI trace interface
+  coverage #(rvvi.ILEN, rvvi.XLEN, rvvi.FLEN, rvvi.VLEN, rvvi.NHART, rvvi.RETIRE) riscvISACOV;
+  initial begin
+    riscvISACOV = new(rvvi);
+    $display("trace2riscvISACOV: coverage initialized");
+  end
+
+  // Dissassemble instruction from RVVI trace for processing by coverage model
+  string disass;
+  dissassembler #(rvvi.XLEN) dissassembler(rvvi.insn[0][0], disass);
+
+  // Invoke the riscvISACOV sample function on each clock edge for the current Instruction
+  // If RVVI accepts more than one instruction or hart, iterate over all of them in the
+  // correct order of retirement (TODO: multiple instructions/harts not implemented)
+  always_ff @(posedge rvvi.clk) begin
+    riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass});
+    $display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass);
+  end
+endmodule
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 6ec35215d..faa3a98b8 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -742,6 +742,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   end
   
   always_ff @(posedge clk) begin
+  $display("wallyTracer: %b", rvvi.insn[0][0]);
 	if(valid) begin
       if(`STD_LOG) begin
         $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 1366b9378..b5f63de67 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -738,8 +738,8 @@ end
 `endif
 
 // Functional coverage
-`ifdef INCLUDE_TRACE2COV
-  trace2cov idv_trace2cov(rvvi); // needed for fcov as of now
+`ifdef FCOV
+  trace2riscvISACOV trace2riscvISACOV(rvvi);
 `endif
 
   ////////////////////////////////////////////////////////////////////////////////
@@ -756,8 +756,6 @@ end
               .CMP_CSR     (1)
               ) idv_trace2api(rvvi);
 
-  // trace2log idv_trace2log(rvvi); // currently not used
-
   string filename;
   initial begin
     // imperasDV requires the elffile be defined at the begining of the simulation.