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https://github.com/openhwgroup/cvw
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Replaced funky rewrite call with file removal
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37716f1b56
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@ -299,7 +299,6 @@ module testbench;
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// Find the test vector files and populate the PC to function label converter
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// Find the test vector files and populate the PC to function label converter
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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logic [P.XLEN-1:0] testadr;
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logic [P.XLEN-1:0] testadr;
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integer memFile;
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always_comb begin
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always_comb begin
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begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
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end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
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@ -331,8 +330,7 @@ module testbench;
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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uartoutfilename = {"logs/",TEST,"_uart.out"};
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uartoutfilename = {"logs/",TEST,"_uart.out"};
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// Initialize uart output file
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// Initialize uart output file
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memFile = $fopen(uartoutfilename, "w"); // Clear existing values in uartFile
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$system("rm ",uartoutfilename); // Clear existing values in uartFile
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$fclose(memFile);
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end
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end
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (riscofTest) begin
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if (riscofTest) begin
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@ -415,6 +413,7 @@ module testbench;
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integer StartIndex;
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integer StartIndex;
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integer EndIndex;
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integer EndIndex;
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integer BaseIndex;
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integer BaseIndex;
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integer memFile;
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integer readResult;
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integer readResult;
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if (P.SDC_SUPPORTED) begin
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if (P.SDC_SUPPORTED) begin
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always @(posedge clk) begin
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always @(posedge clk) begin
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