diff --git a/pipelined/src/fpu/divshiftcalc.sv b/pipelined/src/fpu/divshiftcalc.sv
index e31d60447..bf927ffac 100644
--- a/pipelined/src/fpu/divshiftcalc.sv
+++ b/pipelined/src/fpu/divshiftcalc.sv
@@ -5,7 +5,7 @@ module divshiftcalc(
     input logic  [`FMTBITS-1:0] Fmt,
     input logic Sqrt,
     input logic [`NE+1:0] DivQe,
-    output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt,
+    output logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt,
     output logic [`NORMSHIFTSZ-1:0] DivShiftIn,
     output logic DivResDenorm,
     output logic [`NE+1:0] DivDenormShift
@@ -36,7 +36,7 @@ module divshiftcalc(
     assign NormShift = (`NE+2)'(`NF);
     // if the shift amount is negitive then dont shift (keep sticky bit)
     // need to multiply the early termination shift by LOGR*DIVCOPIES =  left shift of log2(LOGR*DIVCOPIES)
-    assign DivShiftAmt = (DivResDenorm ?  DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, 
+    assign DivShiftAmt = (DivResDenorm ?  DivDenormShift[`LOGNORMSHIFTSZ-1:0]&{`LOGNORMSHIFTSZ{~DivDenormShift[`NE+1]}} : NormShift[`LOGNORMSHIFTSZ-1:0])+{{`LOGNORMSHIFTSZ-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, 
     DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
 
     assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}};
diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv
index a4e01c7ca..75f8795ef 100644
--- a/pipelined/src/fpu/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpostproc.sv
@@ -37,7 +37,7 @@ module fdivsqrtpostproc(
   input logic [`DIVb+1:0] FirstC,
   input logic  Firstqn,
   input logic SqrtM,
-  output logic [`DIVb-(`RADIX/4):0] QmM,
+  output logic [`DIVb-(`RADIX/4):0] QmM, // *** why
   output logic WZero,
   output logic DivSM
 );
@@ -71,6 +71,11 @@ module fdivsqrtpostproc(
 
    // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
   always_comb
-    if(NegSticky) QmM = FirstUM[`DIVb:(`RADIX/4)] << SqrtM;
-    else          QmM = FirstU[`DIVb:(`RADIX/4)]  << SqrtM;
+    if (SqrtM) begin
+      if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << 1;
+      else          QmM = FirstU[`DIVb-(`RADIX/4):0]  << 1;
+    end else begin // divide
+      if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0];
+      else          QmM = FirstU[`DIVb-(`RADIX/4):0];
+    end
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/normshift.sv b/pipelined/src/fpu/normshift.sv
index f382eed37..f2ceb1a35 100644
--- a/pipelined/src/fpu/normshift.sv
+++ b/pipelined/src/fpu/normshift.sv
@@ -65,7 +65,7 @@
     //              - plus 1 to shift out the first 1
 
 module normshift(
-    input logic  [$clog2(`NORMSHIFTSZ)-1:0]      ShiftAmt,   // normalization shift count
+    input logic  [`LOGNORMSHIFTSZ-1:0]      ShiftAmt,   // normalization shift count
     input logic  [`NORMSHIFTSZ-1:0]              ShiftIn,        // is the sum zero
     output logic [`NORMSHIFTSZ-1:0]             Shifted        // is the sum zero
 );
diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv
index 2b5df8e9e..c1be19369 100644
--- a/pipelined/src/fpu/postprocess.sv
+++ b/pipelined/src/fpu/postprocess.sv
@@ -83,7 +83,7 @@ module postprocess (
     logic [`CORRSHIFTSZ-1:0] Mf; // corectly shifted fraction
     logic [`NE+1:0] FullRe;  // Re with bits to determine sign and overflow
     logic UfPlus1;                    // do you add one (for determining underflow flag)
-    logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt;   // normalization shift count
+    logic [`LOGNORMSHIFTSZ-1:0] ShiftAmt;   // normalization shift count
     logic [`NORMSHIFTSZ-1:0] ShiftIn;        // is the sum zero
     logic [`NORMSHIFTSZ-1:0] Shifted;    // the shifted result
     logic Plus1;      // add one to the final result?
@@ -98,7 +98,7 @@ module postprocess (
     logic FmaPreResultDenorm;    // is the result denormalized - calculated before LZA corection
     logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt;   // normalization shift count
     // division singals
-    logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt;
+    logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt;
     logic [`NORMSHIFTSZ-1:0] DivShiftIn;
     logic [`NE+1:0] Qe;
     logic DivByZero;
@@ -156,11 +156,11 @@ module postprocess (
     always_comb
         case(PostProcSel)
             2'b10: begin // fma
-                ShiftAmt = {{$clog2(`NORMSHIFTSZ)-$clog2(3*`NF+7){1'b0}}, FmaShiftAmt};
+                ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(3*`NF+7){1'b0}}, FmaShiftAmt};
                 ShiftIn =  {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+8){1'b0}}};
             end
             2'b00: begin // cvt
-                ShiftAmt = {{$clog2(`NORMSHIFTSZ)-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt};
+                ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt};
                 ShiftIn =  {CvtShiftIn, {`NORMSHIFTSZ-`CVTLEN-`NF-1{1'b0}}};
             end
             2'b01: begin //div
@@ -173,7 +173,7 @@ module postprocess (
                 end
             end
             default: begin 
-                ShiftAmt = {$clog2(`NORMSHIFTSZ){1'bx}}; 
+                ShiftAmt = {`LOGNORMSHIFTSZ{1'bx}}; 
                 ShiftIn = {`NORMSHIFTSZ{1'bx}}; 
             end
         endcase