hptw: Removed NonBusTrapM from LSU

This commit is contained in:
David Harris 2021-07-17 15:22:24 -04:00
parent 428a9c1ca3
commit 2f81e4c70d
4 changed files with 4 additions and 6 deletions

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@ -56,7 +56,6 @@ module lsu
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic DTLBFlushM, input logic DTLBFlushM,
// faults // faults
input logic NonBusTrapM,
output logic DTLBLoadPageFaultM, DTLBStorePageFaultM, output logic DTLBLoadPageFaultM, DTLBStorePageFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM,
// cpu hazard unit (trap) // cpu hazard unit (trap)

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@ -36,7 +36,7 @@ module privileged (
input logic [31:0] InstrD, InstrE, InstrM, InstrW, input logic [31:0] InstrD, InstrE, InstrM, InstrW,
output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] CSRReadValW,
output logic [`XLEN-1:0] PrivilegedNextPCM, output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM, NonBusTrapM, output logic RetM, TrapM,
output logic ITLBFlushF, DTLBFlushM, output logic ITLBFlushF, DTLBFlushM,
input logic InstrValidM, CommittedM, input logic InstrValidM, CommittedM,
input logic FRegWriteM, LoadStallD, input logic FRegWriteM, LoadStallD,

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@ -42,7 +42,7 @@ module trap (
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic StallW, input logic StallW,
input logic InstrValidM, CommittedM, input logic InstrValidM, CommittedM,
output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM, output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
output logic InterruptM, output logic InterruptM,
output logic ExceptionM, output logic ExceptionM,
output logic PendingInterruptM, output logic PendingInterruptM,
@ -56,7 +56,7 @@ module trap (
logic [11:0] PendingIntsM; logic [11:0] PendingIntsM;
//logic InterruptM; //logic InterruptM;
logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
logic BusTrapM; logic NonBusTrapM, BusTrapM;
// Determine pending enabled interrupts // Determine pending enabled interrupts
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9

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@ -58,7 +58,7 @@ module wallypipelinedhart
// logic [1:0] ForwardAE, ForwardBE; // logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, StallE, StallM, StallW; logic StallF, StallD, StallE, StallM, StallW;
logic FlushF, FlushD, FlushE, FlushM, FlushW; logic FlushF, FlushD, FlushE, FlushM, FlushW;
logic RetM, TrapM, NonBusTrapM; logic RetM, TrapM;
// new signals that must connect through DP // new signals that must connect through DP
logic MulDivE, W64E; logic MulDivE, W64E;
@ -215,7 +215,6 @@ module wallypipelinedhart
.STATUS_MPP(STATUS_MPP), // from csr .STATUS_MPP(STATUS_MPP), // from csr
.DTLBFlushM(DTLBFlushM), // connects to privilege .DTLBFlushM(DTLBFlushM), // connects to privilege
.NonBusTrapM(NonBusTrapM), // connects to privilege
.DTLBLoadPageFaultM(DTLBLoadPageFaultM), // connects to privilege .DTLBLoadPageFaultM(DTLBLoadPageFaultM), // connects to privilege
.DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege .DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege
.LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege .LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege