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FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.

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Ross Thompson 2023-06-16 15:40:13 -05:00
parent 509aee36ef
commit 2f35bec970
3 changed files with 9 additions and 6 deletions
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2
fpga/generator/wally.tcl
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@ -23,7 +23,7 @@ if {$board=="ArtyA7"} {
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
} }
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
read_verilog {../src/fpgaTopArtyA7.v} read_verilog {../src/fpgaTopArtyA7.v}
} else { } else {

11
fpga/src/fpgaTop.v
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@ -24,7 +24,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "config.vh"
module fpgaTop module fpgaTop
(input default_250mhz_clk1_0_n, (input default_250mhz_clk1_0_n,
@ -62,6 +62,9 @@ module fpgaTop
output [0 : 0] c0_ddr4_ck_t output [0 : 0] c0_ddr4_ck_t
); );
`include "parameter-defs.vh"
wire CPUCLK; wire CPUCLK;
wire c0_ddr4_ui_clk_sync_rst; wire c0_ddr4_ui_clk_sync_rst;
wire bus_struct_reset; wire bus_struct_reset;
@ -72,12 +75,12 @@ module fpgaTop
wire HCLKOpen; wire HCLKOpen;
wire HRESETnOpen; wire HRESETnOpen;
wire [`AHBW-1:0] HRDATAEXT; wire [P.AHBW-1:0] HRDATAEXT;
wire HREADYEXT; wire HREADYEXT;
wire HRESPEXT; wire HRESPEXT;
wire HSELEXT; wire HSELEXT;
wire [31:0] HADDR; wire [31:0] HADDR;
wire [`AHBW-1:0] HWDATA; wire [P.AHBW-1:0] HWDATA;
wire HWRITE; wire HWRITE;
wire [2:0] HSIZE; wire [2:0] HSIZE;
wire [2:0] HBURST; wire [2:0] HBURST;
@ -211,7 +214,7 @@ module fpgaTop
// wally // wally
wallypipelinedsoc wallypipelinedsoc wallypipelinedsoc #(P) wallypipelinedsoc
(.clk(CPUCLK), (.clk(CPUCLK),
.reset_ext(bus_struct_reset), .reset_ext(bus_struct_reset),
// bus interface // bus interface

2
src/uncore/uncore.sv
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@ -146,7 +146,7 @@ module uncore import cvw::*; #(parameter cvw_t P)(
assign UARTSout = 0; assign UARTIntr = 0; assign UARTSout = 0; assign UARTIntr = 0;
end end
if (P.SDC_SUPPORTED == 1) begin : sdc if (P.SDC_SUPPORTED == 1) begin : sdc
SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, SDC #(P) SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
.HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
// sdc interface // sdc interface
.SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK, .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,