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fixing port errors

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This commit is contained in:
David Harris 2022-07-07 21:57:10 +00:00
parent 0b40f38f02
commit 2f342c430e
3 changed files with 3 additions and 2 deletions
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1
pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.sv vendored
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@ -1 +0,0 @@
/home/jstine/memory/ts1n28hpcpsvtb64x128m4swbaso_180a/VERILOG/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v

1
pipelined/src/wally/wallypipelinedsocwrapper.v
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@ -42,6 +42,7 @@ module wallypipelinedsocwrapper (
output HCLK, HRESETn, output HCLK, HRESETn,
output [31:0] HADDR, output [31:0] HADDR,
output [`AHBW-1:0] HWDATA, output [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB,
output HWRITE, output HWRITE,
output [2:0] HSIZE, output [2:0] HSIZE,
output [2:0] HBURST, output [2:0] HBURST,

3
pipelined/testbench/testbench.sv
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@ -55,6 +55,7 @@ logic [3:0] dummy;
logic HREADYEXT, HRESPEXT; logic HREADYEXT, HRESPEXT;
logic [31:0] HADDR; logic [31:0] HADDR;
logic [`AHBW-1:0] HWDATA; logic [`AHBW-1:0] HWDATA;
logic [`XLEN/8-1:0] HWSTRB;
logic HWRITE; logic HWRITE;
logic [2:0] HSIZE; logic [2:0] HSIZE;
logic [2:0] HBURST; logic [2:0] HBURST;
@ -154,7 +155,7 @@ logic [3:0] dummy;
assign HRDATAEXT = 0; assign HRDATAEXT = 0;
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);