From 2f24249d17959e1f5410f042d10df2c875e87878 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 20 Jan 2021 01:04:28 -0500 Subject: [PATCH] testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64 --- wally-pipelined/src/dmem.sv | 7 ++++- wally-pipelined/src/testbench.sv | 8 ++++-- wally-pipelined/testgen/testgen-ADD-SUB.py | 31 +++++++++++++++------- 3 files changed, 33 insertions(+), 13 deletions(-) diff --git a/wally-pipelined/src/dmem.sv b/wally-pipelined/src/dmem.sv index 8af8fd397..1cab372be 100644 --- a/wally-pipelined/src/dmem.sv +++ b/wally-pipelined/src/dmem.sv @@ -44,7 +44,12 @@ module dmem #(parameter XLEN=32) ( logic [1:0] MemRWdtimM, MemRWclintM, MemRWgpioM; // Address decoding - assign TimEnM = ~(|AdrM[XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF *** check top bits too + generate + if (XLEN == 64) + assign TimEnM = ~(|AdrM[XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x000...80000000 - 0x000...8007FFFF + else + assign TimEnM = AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF + endgenerate assign CLINTEnM = ~(|AdrM[XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF diff --git a/wally-pipelined/src/testbench.sv b/wally-pipelined/src/testbench.sv index 79c3b9807..190a631eb 100644 --- a/wally-pipelined/src/testbench.sv +++ b/wally-pipelined/src/testbench.sv @@ -135,7 +135,9 @@ string tests64iNOc[] = { "rv64i/I-SUBW-01", "3000", "rv64i/I-SW-01", "4000", "rv64i/I-XOR-01", "3000", - "rv64i/I-XORI-01", "3000" + "rv64i/I-XORI-01", "3000", + "rv64i/WALLY-ADD", "4000", + "rv64i/WALLY-SUB", "4000" }; string tests32ic[] = '{ // "rv32ic/WALLY-C-ADHOC-01", "2000", @@ -214,7 +216,9 @@ string tests32i[] = { "rv32i/I-SUB-01","2000", "rv32i/I-SW-01","3000", "rv32i/I-XOR-01","2000", - "rv32i/I-XORI-01","2000" + "rv32i/I-XORI-01","2000", + "rv32i/WALLY-ADD", "3000", + "rv32i/WALLY-SUB", "3000" }; string tests[]; diff --git a/wally-pipelined/testgen/testgen-ADD-SUB.py b/wally-pipelined/testgen/testgen-ADD-SUB.py index 96d56df77..16e02be6b 100755 --- a/wally-pipelined/testgen/testgen-ADD-SUB.py +++ b/wally-pipelined/testgen/testgen-ADD-SUB.py @@ -29,15 +29,15 @@ def computeExpected(a, b, test): # exit(1) def randRegs(): - reg1 = randint(1,32) - reg2 = randint(1,32) - reg3 = randint(1,32) + reg1 = randint(1,31) + reg2 = randint(1,31) + reg3 = randint(1,31) if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): return randRegs() else: return reg1, reg2, reg3 -def writeVector(a,b): +def writeVector(a, b, storecmd): global testnum expected = computeExpected(a, b, test) expected = expected % 2**xlen # drop carry if necessary @@ -50,10 +50,13 @@ def writeVector(a,b): lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" - lines = lines + "sd x" + str(reg3) + ", " + str(8*testnum) + "(x6)\n" + lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n" f.write(lines) - line = formatstr.format(expected)+"\n" + if (xlen == 32): + line = formatrefstr.format(expected)+"\n" + else: + line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" r.write(line) testnum = testnum+1 @@ -74,6 +77,13 @@ seed(0) # make tests reproducible for xlen in xlens: formatstrlen = str(int(xlen/4)) formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number + formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x + if (xlen == 32): + storecmd = "sw" + wordsize = 4 + else: + storecmd = "sd" + wordsize = 8 for test in tests: corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] @@ -101,11 +111,11 @@ for xlen in xlens: # print directed and random test vectors for a in corners: for b in corners: - writeVector(a, b) + writeVector(a, b, storecmd) for i in range(0,numrand): a = getrandbits(xlen) b = getrandbits(xlen) - writeVector(a, b) + writeVector(a, b, storecmd) # print footer @@ -114,8 +124,9 @@ for xlen in xlens: f.write(line) # Finish - line = ".fill " + str(testnum) + ", 8, -1\n" - f.write(line) + lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" + lines = lines + "\nRV_COMPLIANCE_DATA_END\n" + f.write(lines) f.close() r.close()