mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
bbracker
commit
2ef97b9841
@ -1,3 +1,6 @@
|
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IMAGES := ${RISCV}/buildroot/output/images
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||||
DIS := ${IMAGES}/disassembly
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||||
|
||||
all:
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||||
make disassemble
|
||||
make generate
|
||||
@ -7,15 +10,28 @@ generate:
|
||||
dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb
|
||||
|
||||
disassemble:
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||||
mkdir ${RISCV}/buildroot/output/images/disassembly
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||||
# fw_jump
|
||||
riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/fw_jump.elf >> ${RISCV}/buildroot/output/images/disassembly/fw_jump.objdump
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||||
# vmlinux
|
||||
riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/vmlinux >> ${RISCV}/buildroot/output/images/disassembly/vmlinux.objdump
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mkdir -p ${DIS}
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||||
# disassemblies
|
||||
make -j ${DIS}/fw_jump.objdump ${DIS}/vmlinux.objdump ${DIS}/busybox.objdump
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# filesystem
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mkdir ${RISCV}/buildroot/output/images/disassembly/rootfs
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-cd ${RISCV}/buildroot/output/images/disassembly/rootfs; cpio -idv < ../../rootfs.cpio
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make ${DIS}/rootfs/bin/busybox
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# mkdir -p ${DIS}/rootfs
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# -cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio
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|
||||
${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf
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riscv64-unknown-elf-objdump -D ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump
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${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux
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riscv64-unknown-elf-objdump -D ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump
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|
||||
${DIS}/busybox.objdump: ${DIS}/rootfs/bin/busybox
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riscv64-unknown-elf-objdump -D ${DIS}/rootfs/bin/busybox >> ${DIS}/busybox.objdump
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|
||||
${DIS}/rootfs/bin/busybox:
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mkdir -p ${DIS}/rootfs
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-cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio
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|
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clean:
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rm ${RISCV}/buildroot/output/images/wally-virt.dtb
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rm -rf ${RISCV}/buildroot/output/images/disassembly
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rm -f ${IMAGES}/wally-virt.dtb
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rm -rf ${DIS}
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@ -38,6 +38,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084
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|
||||
#-- Run the Simulation
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run -all
|
||||
add log -recursive /*
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do linux-wave.do
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run -all
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|
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@ -76,14 +76,13 @@ module ifu (
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input logic [1:0] STATUS_MPP,
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input logic ITLBWriteF, ITLBFlushF,
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output logic ITLBMissF, InstrDAPageFaultF,
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
|
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output logic InstrAccessFaultF,
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output logic ICacheAccess,
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output logic ICacheMiss
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);
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|
||||
localparam CACHE_ENABLED = `IMEM == `MEM_CACHE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
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logic BranchMisalignedFaultE;
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logic PrivilegedChangePCM;
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@ -120,13 +119,13 @@ module ifu (
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assign PCFExt = {2'b00, PCFSpill};
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|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
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// Spill Support *** add other banners
|
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// Spill Support
|
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/////////////////////////////////////////////////////////////////////////////////////////////
|
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|
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if(`C_SUPPORTED) begin : SpillSupport
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|
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spillsupport spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF,
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.IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill,
|
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.InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill,
|
||||
.SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
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end else begin : NoSpillSupport
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assign PCNextFSpill = PCNextF;
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@ -161,7 +160,7 @@ module ifu (
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
|
||||
|
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end else begin
|
||||
assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF} = '0;
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assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrDAPageFaultF} = '0;
|
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assign PCPF = PCFExt[`PA_BITS-1:0];
|
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assign CacheableF = '1;
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end
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||||
@ -182,8 +181,8 @@ module ifu (
|
||||
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
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|
||||
end else begin : bus
|
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localparam integer WORDSPERLINE = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LINELEN = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS : `XLEN;
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localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LINELEN = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS : `XLEN;
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localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
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logic [LINELEN-1:0] ReadDataLine;
|
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logic [LINELEN-1:0] ICacheBusWriteData;
|
||||
@ -193,7 +192,7 @@ module ifu (
|
||||
logic [31:0] temp;
|
||||
logic SelUncachedAdr;
|
||||
|
||||
busdp #(WORDSPERLINE, LINELEN, LOGWPL)
|
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busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
|
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busdp(.clk, .reset,
|
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.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(),
|
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.LSUBusRead(IFUBusRead), .LSUBusSize(),
|
||||
@ -210,7 +209,7 @@ module ifu (
|
||||
.s(SelUncachedAdr), .y(AllInstrRawF[31:0]));
|
||||
|
||||
|
||||
if(`IMEM == `MEM_CACHE) begin : icache
|
||||
if(CACHE_ENABLED) begin : icache
|
||||
logic [1:0] IFURWF;
|
||||
assign IFURWF = CacheableF ? 2'b10 : 2'b00;
|
||||
|
||||
@ -247,18 +246,28 @@ module ifu (
|
||||
|
||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// PCNextF logic
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
assign PrivilegedChangePCM = RetM | TrapM;
|
||||
|
||||
// *** look at moves pcmux2 and pcmux3 to generates as they are needed only on supporting caches and
|
||||
// privilege instructions respectively.
|
||||
mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
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mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F));
|
||||
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
|
||||
if(CACHE_ENABLED)
|
||||
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM),
|
||||
.y(PCNext2F));
|
||||
else assign PCNext2F = PCNext1F;
|
||||
if(`ZICSR_SUPPORTED)
|
||||
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM),
|
||||
.y(UnalignedPCNextF));
|
||||
else assign UnalignedPCNextF = PCNext2F;
|
||||
|
||||
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
|
||||
flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
|
||||
|
||||
// branch and jump predictor
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Branch and Jump Predictor
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
if (`BPRED_ENABLED) begin : bpred
|
||||
logic BPPredWrongM;
|
||||
logic SelBPPredF;
|
||||
@ -295,6 +304,9 @@ module ifu (
|
||||
else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
|
||||
else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Decode stage pipeline register and compressed instruction decoding.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Decode stage pipeline register and logic
|
||||
flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
|
||||
|
||||
|
||||
@ -42,6 +42,7 @@ module spillsupport (
|
||||
input logic [31:0] InstrRawF,
|
||||
input logic IFUCacheBusStallF,
|
||||
input logic ITLBMissF,
|
||||
input logic InstrDAPageFaultF,
|
||||
output logic [`XLEN-1:0] PCNextFSpill,
|
||||
output logic [`XLEN-1:0] PCFSpill,
|
||||
output logic SelNextSpillF,
|
||||
@ -55,39 +56,36 @@ module spillsupport (
|
||||
logic SpillF;
|
||||
logic SelSpillF, SpillSaveF;
|
||||
logic [15:0] SpillDataLine0;
|
||||
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
|
||||
// *** PLACE ALL THIS IN A MODULE
|
||||
// this exists only if there are compressed instructions.
|
||||
// reuse PC+2/4 circuitry to avoid needing a second CPA to add 2
|
||||
mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
|
||||
mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF), .y(PCNextFSpill));
|
||||
mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}),
|
||||
.s(PCF[1]), .y(PCPlus2F));
|
||||
mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF),
|
||||
.y(PCNextFSpill));
|
||||
mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill));
|
||||
|
||||
assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
|
||||
|
||||
typedef enum logic [1:0] {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF));
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_SPILL_READY;
|
||||
if (reset) CurrState <= #1 STATE_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
|
||||
assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~ITLBMissF;
|
||||
|
||||
always_comb begin
|
||||
case (CurrState)
|
||||
STATE_SPILL_READY: if (TakeSpillF) NextState = STATE_SPILL_SPILL;
|
||||
else NextState = STATE_SPILL_READY;
|
||||
STATE_SPILL_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL_SPILL;
|
||||
else NextState = STATE_SPILL_READY;
|
||||
default: NextState = STATE_SPILL_READY;
|
||||
STATE_READY: if (TakeSpillF) NextState = STATE_SPILL;
|
||||
else NextState = STATE_READY;
|
||||
STATE_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL;
|
||||
else NextState = STATE_READY;
|
||||
default: NextState = STATE_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign SelSpillF = (CurrState == STATE_SPILL_SPILL);
|
||||
assign SelNextSpillF = (CurrState == STATE_SPILL_READY & TakeSpillF) |
|
||||
(CurrState == STATE_SPILL_SPILL & IFUCacheBusStallF);
|
||||
assign SpillSaveF = (CurrState == STATE_SPILL_READY) & TakeSpillF;
|
||||
assign SelSpillF = (CurrState == STATE_SPILL);
|
||||
assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) |
|
||||
(CurrState == STATE_SPILL & IFUCacheBusStallF);
|
||||
assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF;
|
||||
|
||||
flopenr #(16) SpillInstrReg(.clk(clk),
|
||||
.en(SpillSaveF),
|
||||
@ -95,7 +93,8 @@ module spillsupport (
|
||||
.d((`IMEM == `MEM_CACHE) ? InstrRawF[15:0] : InstrRawF[31:16]),
|
||||
.q(SpillDataLine0));
|
||||
|
||||
assign PostSpillInstrRawF = SpillF ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF;
|
||||
mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF),
|
||||
.y(PostSpillInstrRawF));
|
||||
assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, LSU=0)
|
||||
module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
|
||||
(
|
||||
input logic clk, reset,
|
||||
// bus interface
|
||||
@ -66,21 +66,21 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, LSU=0)
|
||||
output logic BusCommittedM);
|
||||
|
||||
|
||||
localparam integer WordCountThreshold = (`DMEM == `MEM_CACHE) ? WORDSPERLINE - 1 : 0;
|
||||
|
||||
localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
|
||||
logic [`PA_BITS-1:0] LocalLSUBusAdr;
|
||||
genvar index;
|
||||
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||
flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
|
||||
.d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
logic [WORDSPERLINE-1:0] CaptureWord;
|
||||
assign CaptureWord[index] = LSUBusAck & LSUBusRead & (index == WordCount);
|
||||
flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA),
|
||||
.q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
end
|
||||
mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr);
|
||||
assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
|
||||
mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M),
|
||||
.s(SelUncachedAdr), .y(LSUBusSize));
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL, (`DMEM == `MEM_CACHE)) // *** cleanup Icache? must fix.
|
||||
busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED)
|
||||
busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
|
||||
.LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead,
|
||||
.DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
|
||||
|
||||
module busfsm #(parameter integer WordCountThreshold,
|
||||
parameter integer LOGWPL, parameter logic CacheEnabled )
|
||||
parameter integer LOGWPL, parameter logic CACHE_ENABLED )
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
|
||||
@ -88,7 +88,7 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]);
|
||||
assign CntEn = PreCntEn & LSUBusAck;
|
||||
|
||||
assign UnCachedAccess = ~CacheEnabled | ~CacheableM;
|
||||
assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) BusCurrState <= #1 STATE_BUS_READY;
|
||||
@ -97,8 +97,8 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
always_comb begin
|
||||
case(BusCurrState)
|
||||
STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
|
||||
else if(LSURWM[0] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_WRITE;
|
||||
else if(LSURWM[1] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_READ;
|
||||
else if(LSURWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE;
|
||||
else if(LSURWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ;
|
||||
else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH;
|
||||
else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE;
|
||||
else BusNextState = STATE_BUS_READY;
|
||||
@ -128,14 +128,14 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
(BusCurrState == STATE_BUS_FETCH) |
|
||||
(BusCurrState == STATE_BUS_WRITE);
|
||||
assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE;
|
||||
assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (LSURWM[0] & ~IgnoreRequest)) |
|
||||
assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_WRITE);
|
||||
assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE);
|
||||
assign LSUBusWriteCrit = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (LSURWM[0])) |
|
||||
assign LSUBusWriteCrit = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
|
||||
(BusCurrState == STATE_BUS_WRITE);
|
||||
|
||||
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (|LSURWM[1] & IgnoreRequest)) |
|
||||
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_READ);
|
||||
assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
|
||||
|
||||
@ -147,5 +147,5 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
|
||||
BusCurrState == STATE_BUS_UNCACHED_WRITE |
|
||||
BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) |
|
||||
~CacheEnabled; // if no dcache always select uncachedadr.
|
||||
~CACHE_ENABLED; // if no dcache always select uncachedadr.
|
||||
endmodule
|
||||
|
||||
@ -31,10 +31,11 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module interlockfsm
|
||||
(input logic clk,
|
||||
module interlockfsm(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic AnyCPUReqM,
|
||||
input logic [1:0] MemRWM,
|
||||
input logic [1:0] AtomicM,
|
||||
input logic ITLBMissOrDAFaultF,
|
||||
input logic ITLBWriteF,
|
||||
input logic DTLBMissOrDAFaultM,
|
||||
@ -48,6 +49,11 @@ module interlockfsm
|
||||
output logic IgnoreRequestTLB,
|
||||
output logic IgnoreRequestTrapM);
|
||||
|
||||
logic ToITLBMiss;
|
||||
logic ToITLBMissNoReplay;
|
||||
logic ToDTLBMiss;
|
||||
logic ToBoth;
|
||||
logic AnyCPUReqM;
|
||||
|
||||
typedef enum logic[2:0] {STATE_T0_READY,
|
||||
STATE_T0_REPLAY,
|
||||
@ -58,6 +64,11 @@ module interlockfsm
|
||||
|
||||
(* mark_debug = "true" *) statetype InterlockCurrState, InterlockNextState;
|
||||
|
||||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||
assign ToITLBMiss = ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & AnyCPUReqM;
|
||||
assign ToITLBMissNoReplay = ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & ~AnyCPUReqM;
|
||||
assign ToDTLBMiss = ~ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM;
|
||||
assign ToBoth = ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) InterlockCurrState <= #1 STATE_T0_READY;
|
||||
@ -66,10 +77,10 @@ module interlockfsm
|
||||
always_comb begin
|
||||
case(InterlockCurrState)
|
||||
STATE_T0_READY: if (TrapM) InterlockNextState = STATE_T0_READY;
|
||||
else if(~ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS;
|
||||
else if(ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS;
|
||||
else if(ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS;
|
||||
else if(ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS;
|
||||
else if(ToDTLBMiss) InterlockNextState = STATE_T3_DTLB_MISS;
|
||||
else if(ToITLBMissNoReplay) InterlockNextState = STATE_T4_ITLB_MISS;
|
||||
else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS;
|
||||
else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS;
|
||||
else InterlockNextState = STATE_T0_READY;
|
||||
STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY;
|
||||
else InterlockNextState = STATE_T0_READY;
|
||||
|
||||
@ -82,6 +82,7 @@ module lsu (
|
||||
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
|
||||
);
|
||||
|
||||
localparam CACHE_ENABLED = `DMEM == `MEM_CACHE;
|
||||
logic [`XLEN+1:0] IEUAdrExtM;
|
||||
logic [`PA_BITS-1:0] LSUPAdrM;
|
||||
logic DTLBMissM;
|
||||
@ -192,9 +193,9 @@ module lsu (
|
||||
.DCacheMiss, .DCacheAccess);
|
||||
assign SelUncachedAdr = '0; // value does not matter.
|
||||
end else begin : bus
|
||||
localparam integer WORDSPERLINE = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS/`XLEN : 1;
|
||||
localparam integer LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN;
|
||||
localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
|
||||
localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1;
|
||||
localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN;
|
||||
localparam integer LOGWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1;
|
||||
logic [LINELEN-1:0] ReadDataLineM;
|
||||
logic [LINELEN-1:0] DCacheBusWriteData;
|
||||
logic [`PA_BITS-1:0] DCacheBusAdr;
|
||||
@ -206,7 +207,7 @@ module lsu (
|
||||
logic SelBus;
|
||||
logic [LOGWPL-1:0] WordCount;
|
||||
|
||||
busdp #(WORDSPERLINE, LINELEN, LOGWPL, 1) busdp(
|
||||
busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(
|
||||
.clk, .reset,
|
||||
.LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
|
||||
.WordCount, .LSUBusWriteCrit,
|
||||
@ -224,7 +225,7 @@ module lsu (
|
||||
.y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset.
|
||||
|
||||
|
||||
if(`DMEM == `MEM_CACHE) begin : dcache
|
||||
if(CACHE_ENABLED) begin : dcache
|
||||
logic [1:0] RW, Atomic;
|
||||
assign RW = CacheableM ? LSURWM : 2'b00; // AND gate
|
||||
assign Atomic = CacheableM ? LSUAtomicM : 2'b00; // AND gate
|
||||
|
||||
@ -78,13 +78,12 @@ module lsuvirtmem(
|
||||
logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
|
||||
logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
|
||||
|
||||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||
assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
|
||||
assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
|
||||
assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
|
||||
assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
|
||||
interlockfsm interlockfsm (
|
||||
.clk, .reset, .AnyCPUReqM, .ITLBMissOrDAFaultF, .ITLBWriteF,
|
||||
.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF,
|
||||
.DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
|
||||
.InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM);
|
||||
hptw hptw( // *** remove logic from (), mention this in style guide CH3
|
||||
|
||||
Loading…
Reference in New Issue
Block a user