From 2eb8721843c4b99b98364275d2b0d7e813da9cea Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 09:35:07 -0800 Subject: [PATCH] continued ZBC integration into ALU --- src/ieu/alu.sv | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 9d945ef8c..088eefb5c 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -39,7 +39,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -90,6 +90,16 @@ module alu #(parameter WIDTH=32) ( else assign ALUResult = FullResult; if (`ZBC_SUPPORTED) begin - + zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); + end + + if (`ZBC_SUPPORTED) begin + always_comb + case ({Funct7, Funct3}) + 10'b0000101_001: Result = ZBCResult; + 10'b0000101_011: Result = ZBCResult; + 10'b0000101_010: Result = ZBCResult; + default: Result = ALUResult; + endcase end else assign Result = ALUResult; endmodule \ No newline at end of file