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Removed the write first sram model.

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This commit is contained in:
Ross Thompson 2022-09-22 16:11:42 -05:00
parent cec50ce208
commit 2eaf3af6c7
1 changed files with 5 additions and 40 deletions
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45
pipelined/src/generic/mem/sram1p1rw.sv
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@ -35,16 +35,7 @@
`include "wally-config.vh" `include "wally-config.vh"
// SRAM is hard sram macro module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
// read first is a verilog model of SRAM with extra hardware to make it appear as write first.
// write first is a verilog model of flops which implements write first behavior.
// If the goal is to use flops use write first. This implements the least amount of hardware for
// the ram. If the goal is to use SRAM use SRAM This currently only supports 64x128 SRAMs.
// If the goal is model SRAM behavior then use READ_FIRST. sram1p1rw adds extra hardware to
// ensure write first behavior is observered.
module sram1p1rw #(parameter DEPTH=128, WIDTH=256, RAM_TYPE = "READ_FIRST") (
input logic clk, input logic clk,
input logic ce, input logic ce,
input logic [$clog2(DEPTH)-1:0] addr, input logic [$clog2(DEPTH)-1:0] addr,
@ -54,14 +45,12 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256, RAM_TYPE = "READ_FIRST") (
output logic [WIDTH-1:0] dout); output logic [WIDTH-1:0] dout);
logic [WIDTH-1:0] RAM[DEPTH-1:0]; logic [WIDTH-1:0] RAM[DEPTH-1:0];
logic [WIDTH-1:0] doutInternal, DinD;
logic weD;
// *************************************************************************** // ***************************************************************************
// TRUE SRAM macro // TRUE SRAM macro
// *************************************************************************** // ***************************************************************************
if (RAM_TYPE == "SRAM") begin if (`USE_SRAM == 1) begin
genvar index; genvar index;
// 64 x 128-bit SRAM // 64 x 128-bit SRAM
// check if the size is ok, complain if not*** // check if the size is ok, complain if not***
@ -71,13 +60,12 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256, RAM_TYPE = "READ_FIRST") (
TS1N28HPCPSVTB64X128M4SW sram( TS1N28HPCPSVTB64X128M4SW sram(
.CLK(clk), .CEB(~ce), .WEB(~we), .CLK(clk), .CEB(~ce), .WEB(~we),
.A(addr), .D(din), .A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(doutInternal)); .BWEB(~BitWriteMask), .Q(dout));
// *************************************************************************** // ***************************************************************************
// Correctly modeled SRAM as read first. Extra hardware to make it behave like // READ first SRAM model
// write first.
// *************************************************************************** // ***************************************************************************
end else if (RAM_TYPE == "READ_FIRST") begin end else begin
integer index2; integer index2;
if (WIDTH%8 != 0) // handle msbs if not a multiple of 8 if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
always_ff @(posedge clk) always_ff @(posedge clk)
@ -95,28 +83,5 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256, RAM_TYPE = "READ_FIRST") (
end end
end end
end end
// ***************************************************************************
// Memory modeled as wrire first. best as flip flop implementation.
// ***************************************************************************
else if (RAM_TYPE == "WRITE_FIRST") begin
logic [$clog2(DEPTH)-1:0] addrD;
flopen #($clog2(DEPTH)) RaddrDelayReg(clk, ce, addr, addrD);
integer index2;
if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
always_ff @(posedge clk)
if (ce & we & bwe[WIDTH/8])
RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
always_ff @(posedge clk) begin
if(ce) begin
if(we) begin
for(index2 = 0; index2 < WIDTH/8; index2++)
if(ce & we & bwe[index2])
RAM[addr][index2*8 +: 8] <= #1 din[index2*8 +: 8];
end
end
end
assign dout = RAM[addrD];
end
endmodule endmodule