From 2e796e3da2846079ce38963c72e090dd87a97755 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 09:41:24 -0700 Subject: [PATCH] lint cleanup: FPU and privileged --- wally-pipelined/src/fpu/fcmp.sv | 1 - wally-pipelined/src/fpu/fma.sv | 1 - wally-pipelined/src/privileged/csr.sv | 8 ++------ wally-pipelined/src/privileged/trap.sv | 5 ++--- 4 files changed, 4 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/fpu/fcmp.sv b/wally-pipelined/src/fpu/fcmp.sv index 93c6b97a5..b47e6eab9 100755 --- a/wally-pipelined/src/fpu/fcmp.sv +++ b/wally-pipelined/src/fpu/fcmp.sv @@ -271,7 +271,6 @@ module exception_cmp_2 ( logic GT; logic LT; logic EQ; - logic [62:0] sixtythreezeros = 63'h0; assign dp = !FOpCtrlE[1]&!FOpCtrlE[0]; assign sp = !FOpCtrlE[1]&FOpCtrlE[0]; diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv index 8849a2581..c4a115a0e 100644 --- a/wally-pipelined/src/fpu/fma.sv +++ b/wally-pipelined/src/fpu/fma.sv @@ -468,7 +468,6 @@ module fma2( logic Plus1, Minus1, CalcPlus1; // do you add or subtract one for rounding logic UfPlus1; // do you add one (for determining underflow flag) logic Invalid,Underflow,Overflow; // flags - logic ZeroSgn; // the result's sign if the sum is zero logic ResultSgnTmp; // the result's sign assuming the result is not zero logic Guard, Round; // bits needed to determine rounding logic UfRound, UfLSBNormSum; // bits needed to determine rounding for underflow flag diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index b995a3bbf..10572a0a1 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -35,9 +35,8 @@ module csr #(parameter input logic clk, reset, input logic FlushD, FlushE, FlushM, FlushW, input logic StallD, StallE, StallM, StallW, - input logic [31:0] InstrD,InstrE,InstrM, - input logic [`XLEN-1:0] PCF, PCD, PCE, PCM, SrcAM, - input logic InterruptM, + input logic [31:0] InstrM, + input logic [`XLEN-1:0] PCM, SrcAM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic TimerIntM, ExtIntM, SwIntM, input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, @@ -51,9 +50,6 @@ module csr #(parameter input logic DCacheAccess, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, - input logic BreakpointFaultM, EcallFaultM, - input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, - input logic LoadMisalignedFaultM, StoreMisalignedFaultM, LoadAccessFaultM, StoreAccessFaultM, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 5814f9152..39be90659 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -4,7 +4,7 @@ // Written: David_Harris@hmc.edu 9 January 2021 // Modified: dottolia@hmc.edu 14 April 2021: Add support for vectored interrupts // -// Purpose: Handle Traps: Exceptions and Interrupt +// Purpose: Handle Traps: Exceptions and Interrupts // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // // A component of the Wally configurable RISC-V project. @@ -27,7 +27,7 @@ `include "wally-config.vh" module trap ( - input logic clk, reset, + input logic reset, input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM, input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM, @@ -40,7 +40,6 @@ module trap ( input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [31:0] InstrM, - input logic StallW, input logic InstrValidM, CommittedM, output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic InterruptM,