From 2e55f1cecc922608e449cc0fe7af2fecb50b758c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 2 Sep 2024 11:19:02 -0700 Subject: [PATCH] Well on the way to a fully automated FPGA build process which correctly sets the clocks and memory locations. --- fpga/generator/Makefile | 10 +++- fpga/generator/ddr4-vcu108.tcl | 3 +- fpga/generator/ddr4-vcu118.tcl | 3 +- fpga/zsbl/Makefile | 7 ++- fpga/zsbl/bios.s | 101 --------------------------------- fpga/zsbl/boot.h | 8 ++- 6 files changed, 24 insertions(+), 108 deletions(-) delete mode 100644 fpga/zsbl/bios.s diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index e311729f6..5f408a57c 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -8,19 +8,22 @@ ArtyA7: export XILINX_PART := xc7a100tcsg324-1 ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1 ArtyA7: export board := ArtyA7 ArtyA7: FPGA_Arty +ArtyA7: CLOCK := 20000000 vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 vcu118: export board := vcu118 vcu118: FPGA_VCU +vcu118: CLOCK := 71000000 vcu108: export XILINX_PART := xcvu095-ffva2104-2-e vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7 vcu108: export board := vcu108 vcu108: FPGA_VCU +vcu108: CLOCK := 50000000 .PHONY: FPGA_Arty FPGA_VCU -FPGA_Arty: PreProcessFiles IP_Arty +FPGA_Arty: PreProcessFiles IP_Arty zsbl vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log FPGA_VCU: PreProcessFiles IP_VCU vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log @@ -60,6 +63,11 @@ PreProcessFiles: sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv +# build the Zero stage boot loader (ZSBL) +.PHONE: zsbl +zsbl: + CLOCK = CLOCK $(MAKE) -C ../zsbl + # Generate Individual IP Blocks $(dst)/%.log: %.tcl mkdir -p IP diff --git a/fpga/generator/ddr4-vcu108.tcl b/fpga/generator/ddr4-vcu108.tcl index 63c849729..c09c115cc 100644 --- a/fpga/generator/ddr4-vcu108.tcl +++ b/fpga/generator/ddr4-vcu108.tcl @@ -1,6 +1,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) +set CPUClock $::env(CLOCK) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 @@ -38,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ diff --git a/fpga/generator/ddr4-vcu118.tcl b/fpga/generator/ddr4-vcu118.tcl index 5a98c07de..a1fbcabbf 100644 --- a/fpga/generator/ddr4-vcu118.tcl +++ b/fpga/generator/ddr4-vcu118.tcl @@ -1,6 +1,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) +set CPUClock $::env(CLOCK) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 @@ -38,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ diff --git a/fpga/zsbl/Makefile b/fpga/zsbl/Makefile index fa22eb607..087da8308 100644 --- a/fpga/zsbl/Makefile +++ b/fpga/zsbl/Makefile @@ -27,11 +27,16 @@ MABI :=-mabi=lp64d LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib LINKER :=linker1000.x +# FGPA parameters +CLOCK ?= 20000000 +MEMSTART ?= 0x80000000 +MEMSIZE ?= 0x10000000 + AFLAGS =$(MARCH) $(MABI) -W # Override directive allows us to prepend other options on the command line # e.g. $ make CFLAGS=-g -override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g +override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g -DSYSTEMCLOCK=${CLOCK} -DMEMSTART=${MEMSTART} -DMEMSIZE=${MEMSIZE} AS=riscv64-unknown-elf-as CC=riscv64-unknown-elf-gcc AR=riscv64-unknown-elf-ar diff --git a/fpga/zsbl/bios.s b/fpga/zsbl/bios.s deleted file mode 100644 index 9a5d6e21f..000000000 --- a/fpga/zsbl/bios.s +++ /dev/null @@ -1,101 +0,0 @@ -PERIOD = 11000000 -#PERIOD = 20 - -.section .init -.global _start -.type _start, @function - - -_start: - # Initialize global pointer - .option push - .option norelax - 1:auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) - .option pop - - li x1, 0 - li x2, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - - # set the stack pointer to the top of memory - 8 bytes (pointer size) - li sp, 0x87FFFFF8 - - li a0, 0x00000000 - li a1, 0x80000000 - #li a2, 128*1024*1024/512 # copy 128MB - li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) - #li a2, 800 # copy 400KB - jal ra, copyFlash - - fence.i - # now toggle led so we know the copy completed. - - # write to gpio - li t2, 0xFF - la t3, 0x1006000C - li t4, 5 - -loop: - - # delay - li t0, PERIOD/2 -delay1: - addi t0, t0, -1 - bge t0, x0, delay1 - sw t2, 0x0(t3) - - li t0, PERIOD/2 -delay2: - addi t0, t0, -1 - bge t0, x0, delay2 - sw x0, 0x0(t3) - - addi t4, t4, -1 - bgt t4, x0, loop - - - # now that the card is copied and the led toggled we - # jump to the copied contents of the sd card. - -jumpToLinux: - csrrs a0, 0xF14, x0 # copy hart ID to a0 - li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB - la a2, end_of_bios - li t0, 0x80000000 # start of code - - jalr x0, t0, 0 - -end_of_bios: - - - - diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h index d86fdd83e..65c4bc5dd 100644 --- a/fpga/zsbl/boot.h +++ b/fpga/zsbl/boot.h @@ -31,6 +31,7 @@ #define WALLYBOOT 10000 #include +#include "system.h" typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ typedef unsigned char BYTE; /* char must be 8-bit */ typedef uint16_t WORD; /* 16-bit unsigned integer */ @@ -44,7 +45,7 @@ typedef QWORD LBA_t; // These locations are copied from the generic configuration // of OpenSBI. These addresses can be found in: // buildroot/output/build/opensbi-0.9/platform/generic/config.mk -#define FDT_ADDRESS 0x87000000 // FW_JUMP_FDT_ADDR +#define FDT_ADDRESS 0xFF000000 // FW_JUMP_FDT_ADDR #define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START #define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR @@ -61,11 +62,12 @@ typedef QWORD LBA_t; // Export disk_read int disk_read(BYTE * buf, LBA_t sector, UINT count); -#define SYSTEMCLOCK 20000000 +//#define SYSTEMCLOCK 50000000 +// *** fix me: now defined in system.h // TODO: This line needs to change back to 20MHz when we fix the // timing problems. -#define MAXSDCCLOCK 5000000 +#define MAXSDCCLOCK 12500000 // Maximum SDC speed is either the system clock divided by 2 (because // of the SPI peripheral clock division) or the maximum speed an SD