mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
changes made with Ross
This commit is contained in:
parent
a5a5b7a408
commit
2e4e5f9c61
@ -5,37 +5,37 @@ add wave -noupdate /testbench/reset
|
|||||||
add wave -noupdate /testbench/reset_ext
|
add wave -noupdate /testbench/reset_ext
|
||||||
add wave -noupdate /testbench/memfilename
|
add wave -noupdate /testbench/memfilename
|
||||||
add wave -noupdate /testbench/dut/core/SATP_REGW
|
add wave -noupdate /testbench/dut/core/SATP_REGW
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM
|
||||||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||||
@ -86,7 +86,6 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
|
|||||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
|
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
|
||||||
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
||||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
|
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
|
||||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
|
|
||||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
|
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
|
||||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
|
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
|
||||||
@ -571,7 +570,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E
|
|||||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
|
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
|
||||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
|
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
|
||||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
|
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
|
||||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE
|
|
||||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
|
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
|
||||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
|
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
|
||||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
|
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
|
||||||
@ -603,8 +601,18 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Br
|
|||||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
|
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
|
||||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
|
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
|
||||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
|
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
|
||||||
|
add wave -noupdate {/testbench/rvvi/csr[0][0][3]}
|
||||||
|
add wave -noupdate {/testbench/rvvi/csr[0][0][1]}
|
||||||
|
add wave -noupdate {/testbench/rvvi/csr_wb[0][0][3]}
|
||||||
|
add wave -noupdate {/testbench/rvvi/csr_wb[0][0][1]}
|
||||||
|
add wave -noupdate {/testbench/rvvi/valid[0][0]}
|
||||||
|
add wave -noupdate /testbench/rvvi/clk
|
||||||
|
add wave -noupdate {/testbench/rvvi/csr[0][0][768]}
|
||||||
|
add wave -noupdate /testbench/rvvi/csr
|
||||||
|
add wave -noupdate {/testbench/rvvi/csr_wb[0][0][768]}
|
||||||
|
add wave -noupdate /testbench/wallyTracer/InstrValidW
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0}
|
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {104199 ns} 0}
|
||||||
quietly wave cursor active 5
|
quietly wave cursor active 5
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 194
|
configure wave -valuecolwidth 194
|
||||||
@ -620,4 +628,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {118528 ns} {128752 ns}
|
WaveRestoreZoom {104186 ns} {104255 ns}
|
||||||
|
@ -65,11 +65,13 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
|
assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
|
||||||
assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
|
assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
|
||||||
|
|
||||||
|
logic valid;
|
||||||
|
|
||||||
always_comb begin
|
always_comb begin
|
||||||
// Since we are detected the CSR change by comparing the old value we need to
|
// Since we are detected the CSR change by comparing the old value we need to
|
||||||
// ensure the CSR is detected when the pipeline's Writeback stage is not
|
// ensure the CSR is detected when the pipeline's Writeback stage is not
|
||||||
// stalled. If it is stalled we want CSRArray to hold the old value.
|
// stalled. If it is stalled we want CSRArray to hold the old value.
|
||||||
if(~StallW) begin
|
if(valid) begin
|
||||||
// machine CSRs
|
// machine CSRs
|
||||||
// *** missing PMP and performance counters.
|
// *** missing PMP and performance counters.
|
||||||
CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
|
CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
|
||||||
@ -202,10 +204,9 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
// Initially connecting the writeback stage signals, but may need to use M stage
|
// Initially connecting the writeback stage signals, but may need to use M stage
|
||||||
// and gate on ~FlushW.
|
// and gate on ~FlushW.
|
||||||
|
|
||||||
logic valid;
|
|
||||||
assign valid = InstrValidW & ~StallW & ~FlushW;
|
assign valid = InstrValidW & ~StallW & ~FlushW;
|
||||||
assign rvvi.clk = clk;
|
assign rvvi.clk = clk;
|
||||||
assign rvvi.valid[0][0] = valid;
|
assign #1 rvvi.valid[0][0] = valid;
|
||||||
assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order
|
assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order
|
||||||
assign rvvi.insn[0][0] = InstrRawW;
|
assign rvvi.insn[0][0] = InstrRawW;
|
||||||
assign rvvi.pc_rdata[0][0] = PCW;
|
assign rvvi.pc_rdata[0][0] = PCW;
|
||||||
@ -231,6 +232,8 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
integer index4;
|
integer index4;
|
||||||
always_ff @(posedge clk) begin
|
always_ff @(posedge clk) begin
|
||||||
for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin
|
for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin
|
||||||
|
// IMPERAS
|
||||||
|
//CSR_W[index4] = (CSRArrayOld[index4] != CSRArray[index4]) ? 1 : 0;
|
||||||
CSRArrayOld[index4] = CSRArray[index4];
|
CSRArrayOld[index4] = CSRArray[index4];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -239,11 +242,16 @@ module wallyTracer(rvviTrace rvvi);
|
|||||||
genvar index5;
|
genvar index5;
|
||||||
for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin
|
for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin
|
||||||
// CSR_W should only indicate the change when the Writeback stage is not stalled and valid.
|
// CSR_W should only indicate the change when the Writeback stage is not stalled and valid.
|
||||||
assign CSR_W[index5] = (CSRArrayOld[index5] != CSRArray[index5]) ? 1 : 0;
|
assign #2 CSR_W[index5] = (CSRArrayOld[index5] != CSRArray[index5]) ? 1 : 0;
|
||||||
assign rvvi.csr_wb[0][0][index5] = CSR_W[index5];
|
assign rvvi.csr_wb[0][0][index5] = CSR_W[index5];
|
||||||
assign rvvi.csr[0][0][index5] = CSRArray[index5];
|
assign rvvi.csr[0][0][index5] = CSRArray[index5];
|
||||||
end
|
end
|
||||||
|
|
||||||
|
// always @rvvi.clk $display("%t @rvvi.clk=%X", $time, rvvi.clk);
|
||||||
|
// always @rvvi.csr[0][0]['h300] $display("%t rvvi.csr[0][0]['h300]=%X", $time, rvvi.csr[0][0]['h300]);
|
||||||
|
// always @rvvi.csr_wb[0][0]['h300] $display("%t rvvi.csr_wb[0][0]['h300]=%X", $time, rvvi.csr_wb[0][0]['h300]);
|
||||||
|
// always @rvvi.valid[0][0] $display("%t rvvi.valid[0][0]=%X", $time, rvvi.valid[0][0]);
|
||||||
|
|
||||||
// *** implementation only cancel? so sc does not clear?
|
// *** implementation only cancel? so sc does not clear?
|
||||||
assign rvvi.lrsc_cancel[0][0] = '0;
|
assign rvvi.lrsc_cancel[0][0] = '0;
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user