From 337e40ac1b24da65e28607a3c9b0cf1109d796ce Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jul 2024 06:59:58 -0700 Subject: [PATCH 1/4] Issue #894: trap on floating-point ops with reserved rounding modes --- src/fpu/fctrl.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 8595fd29e..eed90ddcf 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -81,6 +81,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( logic [1:0] Fmt, Fmt2; // format - before possible reduction logic SupportedFmt; // is the format supported logic SupportedFmt2; // is the source format supported for fp -> fp + logic SupportedRM; // is the rounding mode supported logic FCvtIntD, FCvtIntM; // convert to integer operation logic ZfaD; // Zfa variants of instructions logic ZfaFRoundNXD; // Zfa froundnx instruction @@ -93,14 +94,16 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( (Fmt == 2'b10 & P.ZFH_SUPPORTED) | (Fmt == 2'b11 & P.Q_SUPPORTED)); assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) | (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED)); + // rounding modes 5 and 6 are reserved. Rounding mode 7 is dynamic, and is reserved if FRM is 5, 6, or 7 + assign SupportedRM = ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))); // decode the instruction // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt_Zfa_FroundNX always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; - else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) - ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // for anything other than loads and stores, check for supported format + else if (OpD != 7'b0000111 & OpD != 7'b0100111 & (~SupportedFmt | ~SupportedRM)) + ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // for anything other than loads and stores, check for supported format and rounding mode else begin ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // default: non-implemented instruction /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed From 7234abebef08a5d28887d700f7a4998cd3926143 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jul 2024 09:09:13 -0700 Subject: [PATCH 2/4] Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt --- src/fpu/fctrl.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index eed90ddcf..ab9cad093 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -95,8 +95,11 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) | (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED)); // rounding modes 5 and 6 are reserved. Rounding mode 7 is dynamic, and is reserved if FRM is 5, 6, or 7 - assign SupportedRM = ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))); - + assign SupportedRM = ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))) | + (OpD == 7'b1010011 & Funct3D == 3'b101 & Funct7D[6:2] == 5'b10100 & P.ZFA_SUPPORTED); // Zfa fltq has a funny rounding mode + /*assign SupportedRM = ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))) | + (OpD == 7'b1010011 & P.ZFA_SUPPORTED); +*/ // decode the instruction // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt_Zfa_FroundNX always_comb From c637e40058c9e48331fc1c366b51348410eb158f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jul 2024 09:19:23 -0700 Subject: [PATCH 3/4] CHeck legal rnum field when decoding aes64ks1i --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index d482616ef..d4a8afe23 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -238,7 +238,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( if ((P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) & P.XLEN == 64) begin // ZKND and ZKNE shared instructions casez({OpD, Funct7D, Funct3D}) - 17'b0010011_0011000_001: if (Rs2D[4] == 1'b1) + 17'b0010011_0011000_001: if (Rs2D[4] == 1'b1 & $unsigned(Rs2D[3:0]) <= 10) BMUControlsD = `BMUCTRLW'b000_0111_0010_1_0_0_0_1_0_0_0_0_0; // aes64ks1i - key schedule istr1 17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_0_1_0_0_0_0_0; // aes64ks2 - key schedule istr2 endcase From 7360be1234ff6b1db7c50b1df8273381f67ac04c Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jul 2024 09:43:54 -0700 Subject: [PATCH 4/4] Legalized PMPconfig WARL --- src/privileged/csrm.sv | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index f86b3f6d6..24132ab93 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -106,7 +106,10 @@ module csrm import cvw::*; #(parameter cvw_t P) ( genvar i; if (P.PMP_ENTRIES > 0) begin:pmp logic [P.PMP_ENTRIES-1:0] WritePMPCFGM; - logic [P.PMP_ENTRIES-1:0] WritePMPADDRM ; + logic [P.PMP_ENTRIES-1:0] WritePMPADDRM; + logic [7:0] CSRPMPWriteValM[P.PMP_ENTRIES-1:0]; + logic [7:0] CSRPMPLegalizedWriteValM[P.PMP_ENTRIES-1:0]; + logic [1:0] CSRPMPWRLegalizedWriteValM[P.PMP_ENTRIES-1:0]; logic [P.PMP_ENTRIES-1:0] ADDRLocked, CFGLocked; for(i=0; i