diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index d138a933a..730651721 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -123,6 +123,9 @@ module lsu
   logic 		       HPTWStall;  
   logic [`XLEN-1:0] 	       HPTWPAdrE;
   logic [`XLEN-1:0] 	       HPTWPAdrM;  
+  logic [`XLEN-1:0] TranslationVAdr;
+  logic [`PA_BITS-1:0] TranslationPAdr;
+  logic            UseTranslationVAdr;
   logic 		       HPTWRead;
   logic [1:0] 		       MemRWMtoDCache;
   logic [2:0] 		       Funct3MtoDCache;
@@ -162,15 +165,25 @@ module lsu
 				  .DTLBWriteM(DTLBWriteM),
 				  .HPTWReadPTE(HPTWReadPTE),
 				  .HPTWStall(HPTWStall),
-				  .HPTWPAdrE(HPTWPAdrE),
-				  .HPTWPAdrM(HPTWPAdrM),				  
+//				  .HPTWPAdrE(HPTWPAdrE),
+//				  .HPTWPAdrM(HPTWPAdrM),	
+          .TranslationVAdr,
+          .TranslationPAdr,			  
+          .UseTranslationVAdr,
 				  .HPTWRead(HPTWRead),
 				  .SelPTW(SelPTW),
 				  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
 				  .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
 				  .WalkerStorePageFaultM(WalkerStorePageFaultM));
 
-//  assign PageTableEntryF = PTE;
+  logic [`XLEN-1:0] TranslationPAdrXLEN;
+  generate // *** needs fixing about truncation dh 7/17/21
+    if (`XLEN == 32) assign TranslationPAdrXLEN = TranslationPAdr[31:0];
+    else             assign TranslationPAdrXLEN = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
+  endgenerate
+  mux2 #(`XLEN) HPTWPAdrMux(TranslationPAdrXLEN, TranslationVAdr, UseTranslationVAdr, HPTWPAdrE); // *** misleading to call it PAdr, bad because some bits have been truncated
+  flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);  // *** perhaps HPTW should just send PAdrE, and LSU can latch it as necessary
+
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index 85a76482a..554a0605f 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -42,8 +42,11 @@ module pagetablewalker
    output logic [1:0]	    PageType, // page type to TLBs
    output logic		    ITLBWriteF, DTLBWriteM, // write TLB with new entry
    output logic 	    SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU
-   output logic [`XLEN-1:0] HPTWPAdrE, // *** this really needs to be 34 bits for RV32 and 64 bits for RV64.  Impacts lots of stuff in LSU and D$.  On Ross's list to investigate.  7/17/21
-   output logic [`XLEN-1:0] HPTWPAdrM, // *** same
+   //output logic [`XLEN-1:0] HPTWPAdrE, // *** this really needs to be 34 bits for RV32 and 64 bits for RV64.  Impacts lots of stuff in LSU and D$.  On Ross's list to investigate.  7/17/21
+   //output logic [`XLEN-1:0] HPTWPAdrM, // *** same
+   output logic [`XLEN-1:0]		    TranslationVAdr,
+   output logic [`PA_BITS-1:0]	    TranslationPAdr,
+   output logic                     UseTranslationVAdr,
    output logic		    HPTWRead, // HPTW requesting to read memory
    output logic		    WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
 );
@@ -53,9 +56,8 @@ module pagetablewalker
       // Internal signals
       logic			    DTLBWalk; // register TLBs translation miss requests
       logic [`PPN_BITS-1:0]	    BasePageTablePPN;
-      logic [`XLEN-1:0]		    TranslationVAdr;
-      logic [`PA_BITS-1:0]	    TranslationPAdr;
       logic [`PPN_BITS-1:0]	    CurrentPPN;
+	  logic [`XLEN-1:0] HPTWPAdrE; // ***delete when done
       logic			    MemWrite;
       logic			    Executable, Writable, Readable, Valid;
 	  logic 			MegapageMisaligned, GigapageMisaligned, TerapageMisaligned;
@@ -83,7 +85,7 @@ module pagetablewalker
       assign CurrentPPN = PTE[`PPN_BITS+9:10];
 
 	  // State flops
-      flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);  // *** perhaps HPTW should just send PAdrE, and LSU can latch it as necessary
+      //flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);  // *** perhaps HPTW should just send PAdrE, and LSU can latch it as necessary
 	  flopenrc #(1) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, DTLBMissM, DTLBWalk); // track whether walk is for DTLB or ITLB
 	  flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
 	
@@ -103,6 +105,7 @@ module pagetablewalker
 	  assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
 	  assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
 	  assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
+	  assign UseTranslationVAdr = (NextWalkerState == LEAF) || (WalkerState == LEAF);
 
 	  // Raise faults.  DTLBMiss
 	  assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk;
@@ -219,8 +222,9 @@ module pagetablewalker
 		end
 	  endcase
     end else begin // No Virtual memory supported; tie HPTW outputs to 0
-      assign HPTWPAdrE = 0; assign HPTWRead = 0; assign SelPTW = 0;
+      assign HPTWRead = 0; assign SelPTW = 0;
       assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
+	  //assign HPTWPAdrE = 0; // comment out ***, replace with Translate P/V, control signal
     end
   endgenerate
 endmodule