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Adding RISC-V Assertions

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Huda-10xe 2025-02-06 23:47:43 -08:00
parent 737d624a0d
commit 2db536bf49
1 changed files with 5 additions and 1 deletions
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6
testbench/testbench.sv
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@ -28,6 +28,7 @@
`include "config.vh" `include "config.vh"
`include "tests.vh" `include "tests.vh"
`include "BranchPredictorType.vh" `include "BranchPredictorType.vh"
// `include "RV32VM_coverage copy.sv"
`ifdef USE_IMPERAS_DV `ifdef USE_IMPERAS_DV
`include "idv/idv.svh" `include "idv/idv.svh"
@ -292,7 +293,8 @@ module testbench;
# 100; # 100;
TestBenchReset = 1'b0; TestBenchReset = 1'b0;
end end
mcount u_mcounteren_checker (
);
always_ff @(posedge clk) always_ff @(posedge clk)
if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET; if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
else CurrState <= NextState; else CurrState <= NextState;
@ -751,6 +753,8 @@ end
.CMP_CSR (1) .CMP_CSR (1)
) idv_trace2api(rvvi); ) idv_trace2api(rvvi);
`include "RV_Assertions.sv"
string filename; string filename;
initial begin initial begin
// imperasDV requires the elffile be defined at the begining of the simulation. // imperasDV requires the elffile be defined at the begining of the simulation.