diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 710775968..e29ef3efe 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -73,7 +73,7 @@ module bpred (
   logic [1:0]               DirPredictionF;
 
   logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
-  logic [`XLEN-1:0]         PredPCF, RASPCF;
+  logic [`XLEN-1:0]         BTAF, RASPCF;
   logic                     PredictionPCWrongE;
   logic                     AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
   logic [3:0]               InstrClassD;
@@ -90,7 +90,7 @@ module bpred (
   logic 					RASTargetWrongE;
   logic 					JumpOrTakenBranchE;
 
-  logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
+  logic [`XLEN-1:0] BTAD, BTAE, RASPCD, RASPCE;
 
   // Part 1 branch direction prediction
   // look into the 2 port Sram model. something is wrong. 
@@ -142,7 +142,7 @@ module bpred (
   btb #(`BTB_SIZE) 
     TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
           .PCNextF, .PCF, .PCD, .PCE, .PCM,
-          .PredPCF,
+          .BTAF, .BTAD,
           .BTBPredInstrClassF,
           .PredictionInstrClassWrongM,
           .IEUAdrE, .IEUAdrM,
@@ -189,7 +189,7 @@ module bpred (
 							.PredInstrClassF, .InstrClassD, .InstrClassE,
 							.WrongPredInstrClassD, .RASPCF, .PCLinkE);
 
-  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
+  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTAF;
 
   assign InstrClassD[0] = BranchD;
   assign InstrClassD[1] = JumpD ;
@@ -249,19 +249,18 @@ module bpred (
   // 3. target ras    (ras target wrong / class[2])
   // 4. direction     (br dir wrong / class[0])
 
-  // Unforuantely we can't relay on PCD to infer the correctness of the BTB or RAS because the class prediction 
+  // Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction 
   // could be wrong or the fall through address selected for branch predict not taken.
   // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
   // both without the above inaccuracies.
-  assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE;
+  assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE;
   assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
 
   assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1];
   
   flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
 
-  flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
-  flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE);
+  flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE);
 
   flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
   flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 8e2d0e259..2bb006714 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -31,19 +31,20 @@
 `include "wally-config.vh"
 
 module btb #(parameter Depth = 10 ) (
-  input logic 			   clk,
-  input logic 			   reset,
-  input logic 			   StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
-  input logic [`XLEN-1:0]  PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
-  output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
+  input  logic 			   clk,
+  input  logic 			   reset,
+  input  logic 			   StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
+  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
+  output logic [`XLEN-1:0] BTAF, // BTB's guess at PC
+  output logic [`XLEN-1:0] BTAD,  
   output logic [3:0] 	   BTBPredInstrClassF, // BTB's guess at instruction class
   // update
-  input logic 			   PredictionInstrClassWrongM, // BTB's instruction class guess was wrong
-  input logic [`XLEN-1:0]  IEUAdrE, // Branch/jump target address to insert into btb
-  input logic [`XLEN-1:0]  IEUAdrM, // Branch/jump target address to insert into btb
-  input logic [3:0] 	   InstrClassD, // Instruction class to insert into btb
-  input logic [3:0] 	   InstrClassE, // Instruction class to insert into btb
-  input logic [3:0] 	   InstrClassM                            // Instruction class to insert into btb
+  input  logic 			   PredictionInstrClassWrongM, // BTB's instruction class guess was wrong
+  input  logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
+  input  logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb
+  input  logic [3:0] 	   InstrClassD, // Instruction class to insert into btb
+  input  logic [3:0] 	   InstrClassE, // Instruction class to insert into btb
+  input  logic [3:0] 	   InstrClassM                            // Instruction class to insert into btb
 );
 
   logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex;
@@ -51,7 +52,6 @@ module btb #(parameter Depth = 10 ) (
   logic 					MatchF, MatchD, MatchE, MatchM, MatchNextX, MatchXF;
   logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
   logic [`XLEN+3:0] 		TableBTBPredictionF;
-  logic [`XLEN-1:0] 		PredPCD;  
   logic 					UpdateEn;
     
   // hashing function for indexing the PC
@@ -78,14 +78,14 @@ module btb #(parameter Depth = 10 ) (
   
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
-  assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
-                                MatchD ? {InstrClassD, PredPCD} :
+  assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, BTAF} :
+                                MatchD ? {InstrClassD, BTAD} :
                                 MatchE ? {InstrClassE, IEUAdrE} :
                                 {InstrClassM, IEUAdrM} ;
 
   flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
 
-  assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF};
+  assign {BTBPredInstrClassF, BTAF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF};
 
 
   assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
@@ -95,6 +95,6 @@ module btb #(parameter Depth = 10 ) (
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
      .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
 
-  flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
+  flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BTAF, BTAD);
 
 endmodule