From 2d8ccbd4ead1dbae7f3aadc6d98981c0446e6da1 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 12 May 2022 22:00:23 +0000
Subject: [PATCH] More trap/csr simplification

---
 pipelined/src/privileged/csr.sv        | 3 ++-
 pipelined/src/privileged/privileged.sv | 3 ---
 pipelined/src/privileged/trap.sv       | 1 -
 3 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index b9ed77e4c..c6eec2113 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -59,7 +59,7 @@ module csr #(parameter
   input  logic             SelHPTW,
   output logic [1:0]       STATUS_MPP,
   output logic             STATUS_SPP, STATUS_TSR, STATUS_TVM,
-  output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW,
+  output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, 
   output logic [`XLEN-1:0]      MEDELEG_REGW, 
   output logic [`XLEN-1:0] SATP_REGW,
   output logic [11:0]      MIP_REGW, MIE_REGW, MIDELEG_REGW,
@@ -83,6 +83,7 @@ module csr #(parameter
 (* mark_debug = "true" *)  logic [`XLEN-1:0] CSRWriteValM;
  
 (* mark_debug = "true" *)  logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
+  logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW;
   logic [31:0]     MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
   logic            WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
   logic            CSRMWriteM, CSRSWriteM, CSRUWriteM;
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 44c4f4f6f..61241b178 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -82,7 +82,6 @@ module privileged (
 );
 
   logic [`XLEN-1:0] CauseM;
-  logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW;
   logic [`XLEN-1:0] MEDELEG_REGW;
   logic [11:0]      MIDELEG_REGW;
 
@@ -136,7 +135,6 @@ module privileged (
           .CauseM, .SelHPTW,
           .STATUS_MPP,
           .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
-          .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
           .MEDELEG_REGW, 
           .SATP_REGW,
           .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
@@ -161,7 +159,6 @@ module privileged (
             .LoadPageFaultM, .StoreAmoPageFaultM,
             .mretM, .sretM, 
             .PrivilegeModeW, .NextPrivilegeModeM,
-            .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
             .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
             .STATUS_MIE, .STATUS_SIE,
             .InstrValidM, .CommittedM,  
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index 1566ce411..47fdb977f 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -39,7 +39,6 @@ module trap (
   (* mark_debug = "true" *) input logic 		   LoadPageFaultM, StoreAmoPageFaultM,
   (* mark_debug = "true" *) input logic 		   mretM, sretM, 
   input logic [1:0] 	   PrivilegeModeW, NextPrivilegeModeM,
-  (* mark_debug = "true" *) input logic [`XLEN-1:0]  MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW,
   (* mark_debug = "true" *) input logic [11:0] 	   MIP_REGW, MIE_REGW, MIDELEG_REGW,
   input logic 		   STATUS_MIE, STATUS_SIE,
   input logic 		   InstrValidM, CommittedM,