mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
More work toward riscof tests
This commit is contained in:
David Harris
parent
c6a58eb5b6
commit
2d7f4b133c
@ -64,7 +64,7 @@ tc = TestCase(
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grepstr="400100000 instructions")
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configs.append(tc)
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tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64periph", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
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tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64f", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64periph", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
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for test in tests64gc:
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tc = TestCase(
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name=test,
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@ -73,7 +73,7 @@ for test in tests64gc:
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grepstr="All tests ran without failures")
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configs.append(tc)
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tests32gc = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32m", "wally32a", "imperas32c", "wally32priv", "wally32periph"] #, "imperas32mmu""wally32i",
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tests32gc = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "arch32d", "imperas32i", "imperas32f", "imperas32m", "wally32a", "imperas32c", "wally32priv", "wally32periph"] #, "imperas32mmu""wally32i",
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for test in tests32gc:
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tc = TestCase(
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name=test,
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@ -89,6 +89,7 @@ logic [3:0] dummy;
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if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
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else tests = {arch64c};
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"arch64m": if (`M_SUPPORTED) tests = arch64m;
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"arch64f": if (`D_SUPPORTED) tests = arch64f;
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"arch64d": if (`D_SUPPORTED) tests = arch64d;
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"imperas64i": tests = imperas64i;
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"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
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@ -112,9 +113,9 @@ logic [3:0] dummy;
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else tests = {arch32c};
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"arch32m": if (`M_SUPPORTED) tests = arch32m;
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"arch32f": if (`F_SUPPORTED) tests = arch32f;
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"arch32d": if (`D_SUPPORTED) tests = arch32d;
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"imperas32i": tests = imperas32i;
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"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
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// "wally32d": if (`D_SUPPORTED) tests = wally32d;
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"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
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"wally32a": if (`A_SUPPORTED) tests = wally32a;
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"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
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@ -1052,35 +1052,186 @@ string imperas32f[] = '{
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"rv64i_m/I/src/xori-01.S"
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};
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string arch64f[] = '{
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`RISCVARCHTEST,
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"rv64i_m/F/src/fadd_b10-01.S",
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"rv64i_m/F/src/fadd_b1-01.S",
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"rv64i_m/F/src/fadd_b11-01.S",
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"rv64i_m/F/src/fadd_b12-01.S",
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"rv64i_m/F/src/fadd_b13-01.S",
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"rv64i_m/F/src/fadd_b2-01.S",
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"rv64i_m/F/src/fadd_b3-01.S",
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"rv64i_m/F/src/fadd_b4-01.S",
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"rv64i_m/F/src/fadd_b5-01.S",
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"rv64i_m/F/src/fadd_b7-01.S",
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"rv64i_m/F/src/fadd_b8-01.S",
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"rv64i_m/F/src/fclass_b1-01.S",
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"rv64i_m/F/src/fcvt.s.w_b25-01.S",
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"rv64i_m/F/src/fcvt.s.w_b26-01.S",
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"rv64i_m/F/src/fcvt.s.wu_b25-01.S",
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"rv64i_m/F/src/fcvt.s.wu_b26-01.S",
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"rv64i_m/F/src/fcvt.w.s_b1-01.S",
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"rv64i_m/F/src/fcvt.w.s_b22-01.S",
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"rv64i_m/F/src/fcvt.w.s_b23-01.S",
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"rv64i_m/F/src/fcvt.w.s_b24-01.S",
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"rv64i_m/F/src/fcvt.w.s_b27-01.S",
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"rv64i_m/F/src/fcvt.w.s_b28-01.S",
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"rv64i_m/F/src/fcvt.w.s_b29-01.S",
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"rv64i_m/F/src/fcvt.wu.s_b1-01.S",
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"rv64i_m/F/src/fcvt.wu.s_b22-01.S",
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"rv64i_m/F/src/fcvt.wu.s_b23-01.S",
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"rv64i_m/F/src/fcvt.wu.s_b24-01.S",
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"rv64i_m/F/src/fcvt.wu.s_b27-01.S",
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"rv64i_m/F/src/fcvt.wu.s_b28-01.S",
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"rv64i_m/F/src/fcvt.wu.s_b29-01.S",
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"rv64i_m/F/src/fdiv_b1-01.S",
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"rv64i_m/F/src/fdiv_b20-01.S",
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"rv64i_m/F/src/fdiv_b2-01.S",
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"rv64i_m/F/src/fdiv_b21-01.S",
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"rv64i_m/F/src/fdiv_b3-01.S",
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"rv64i_m/F/src/fdiv_b4-01.S",
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"rv64i_m/F/src/fdiv_b5-01.S",
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"rv64i_m/F/src/fdiv_b6-01.S",
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"rv64i_m/F/src/fdiv_b7-01.S",
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"rv64i_m/F/src/fdiv_b8-01.S",
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"rv64i_m/F/src/fdiv_b9-01.S",
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"rv64i_m/F/src/feq_b1-01.S",
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"rv64i_m/F/src/feq_b19-01.S",
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"rv64i_m/F/src/fle_b1-01.S",
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"rv64i_m/F/src/fle_b19-01.S",
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"rv64i_m/F/src/flt_b1-01.S",
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"rv64i_m/F/src/flt_b19-01.S",
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// "rv64i_m/F/src/flw-align-01.S",
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"rv64i_m/F/src/fmadd_b1-01.S",
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"rv64i_m/F/src/fmadd_b14-01.S",
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// "rv64i_m/F/src/fmadd_b15-01.S",
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"rv64i_m/F/src/fmadd_b16-01.S",
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"rv64i_m/F/src/fmadd_b17-01.S",
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"rv64i_m/F/src/fmadd_b18-01.S",
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"rv64i_m/F/src/fmadd_b2-01.S",
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"rv64i_m/F/src/fmadd_b3-01.S",
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"rv64i_m/F/src/fmadd_b4-01.S",
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"rv64i_m/F/src/fmadd_b5-01.S",
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"rv64i_m/F/src/fmadd_b6-01.S",
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"rv64i_m/F/src/fmadd_b7-01.S",
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"rv64i_m/F/src/fmadd_b8-01.S",
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"rv64i_m/F/src/fmax_b1-01.S",
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"rv64i_m/F/src/fmax_b19-01.S",
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"rv64i_m/F/src/fmin_b1-01.S",
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"rv64i_m/F/src/fmin_b19-01.S",
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"rv64i_m/F/src/fmsub_b1-01.S",
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"rv64i_m/F/src/fmsub_b14-01.S",
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"rv64i_m/F/src/fmsub_b15-01.S",
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"rv64i_m/F/src/fmsub_b16-01.S",
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"rv64i_m/F/src/fmsub_b17-01.S",
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"rv64i_m/F/src/fmsub_b18-01.S",
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"rv64i_m/F/src/fmsub_b2-01.S",
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"rv64i_m/F/src/fmsub_b3-01.S",
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"rv64i_m/F/src/fmsub_b4-01.S",
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"rv64i_m/F/src/fmsub_b5-01.S",
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"rv64i_m/F/src/fmsub_b6-01.S",
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"rv64i_m/F/src/fmsub_b7-01.S",
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"rv64i_m/F/src/fmsub_b8-01.S",
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"rv64i_m/F/src/fmul_b1-01.S",
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"rv64i_m/F/src/fmul_b2-01.S",
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"rv64i_m/F/src/fmul_b3-01.S",
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"rv64i_m/F/src/fmul_b4-01.S",
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"rv64i_m/F/src/fmul_b5-01.S",
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"rv64i_m/F/src/fmul_b6-01.S",
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"rv64i_m/F/src/fmul_b7-01.S",
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"rv64i_m/F/src/fmul_b8-01.S",
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"rv64i_m/F/src/fmul_b9-01.S",
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"rv64i_m/F/src/fmv.w.x_b25-01.S",
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"rv64i_m/F/src/fmv.w.x_b26-01.S",
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"rv64i_m/F/src/fmv.x.w_b1-01.S",
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"rv64i_m/F/src/fmv.x.w_b22-01.S",
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"rv64i_m/F/src/fmv.x.w_b23-01.S",
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"rv64i_m/F/src/fmv.x.w_b24-01.S",
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"rv64i_m/F/src/fmv.x.w_b27-01.S",
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"rv64i_m/F/src/fmv.x.w_b28-01.S",
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"rv64i_m/F/src/fmv.x.w_b29-01.S",
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"rv64i_m/F/src/fnmadd_b1-01.S",
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"rv64i_m/F/src/fnmadd_b14-01.S",
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// "rv64i_m/F/src/fnmadd_b15-01.S",
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"rv64i_m/F/src/fnmadd_b16-01.S",
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"rv64i_m/F/src/fnmadd_b17-01.S",
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"rv64i_m/F/src/fnmadd_b18-01.S",
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"rv64i_m/F/src/fnmadd_b2-01.S",
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"rv64i_m/F/src/fnmadd_b3-01.S",
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"rv64i_m/F/src/fnmadd_b4-01.S",
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"rv64i_m/F/src/fnmadd_b5-01.S",
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"rv64i_m/F/src/fnmadd_b6-01.S",
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"rv64i_m/F/src/fnmadd_b7-01.S",
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"rv64i_m/F/src/fnmadd_b8-01.S",
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"rv64i_m/F/src/fnmsub_b1-01.S",
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"rv64i_m/F/src/fnmsub_b14-01.S",
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// "rv64i_m/F/src/fnmsub_b15-01.S",
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"rv64i_m/F/src/fnmsub_b16-01.S",
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"rv64i_m/F/src/fnmsub_b17-01.S",
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"rv64i_m/F/src/fnmsub_b18-01.S",
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"rv64i_m/F/src/fnmsub_b2-01.S",
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"rv64i_m/F/src/fnmsub_b3-01.S",
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"rv64i_m/F/src/fnmsub_b4-01.S",
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"rv64i_m/F/src/fnmsub_b5-01.S",
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"rv64i_m/F/src/fnmsub_b6-01.S",
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"rv64i_m/F/src/fnmsub_b7-01.S",
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"rv64i_m/F/src/fnmsub_b8-01.S",
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"rv64i_m/F/src/fsgnj_b1-01.S",
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"rv64i_m/F/src/fsgnjn_b1-01.S",
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"rv64i_m/F/src/fsgnjx_b1-01.S",
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// "rv64i_m/F/src/fsqrt_b1-01.S",
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// "rv64i_m/F/src/fsqrt_b20-01.S",
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// "rv64i_m/F/src/fsqrt_b2-01.S",
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// "rv64i_m/F/src/fsqrt_b3-01.S",
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// "rv64i_m/F/src/fsqrt_b4-01.S",
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// "rv64i_m/F/src/fsqrt_b5-01.S",
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// "rv64i_m/F/src/fsqrt_b7-01.S",
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// "rv64i_m/F/src/fsqrt_b8-01.S",
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// "rv64i_m/F/src/fsqrt_b9-01.S",
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"rv64i_m/F/src/fsub_b10-01.S",
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"rv64i_m/F/src/fsub_b1-01.S",
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"rv64i_m/F/src/fsub_b11-01.S",
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"rv64i_m/F/src/fsub_b12-01.S",
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"rv64i_m/F/src/fsub_b13-01.S",
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"rv64i_m/F/src/fsub_b2-01.S",
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"rv64i_m/F/src/fsub_b3-01.S",
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"rv64i_m/F/src/fsub_b4-01.S",
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"rv64i_m/F/src/fsub_b5-01.S",
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"rv64i_m/F/src/fsub_b7-01.S",
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"rv64i_m/F/src/fsub_b8-01.S"
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// "rv64i_m/F/src/fsw-align-01.S"
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};
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string arch64d[] = '{
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`RISCVARCHTEST,
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"rv32i_m/D/src/fadd.d_b10-01.S",
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"rv32i_m/D/src/fadd.d_b1-01.S",
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"rv32i_m/D/src/fadd.d_b11-01.S",
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"rv32i_m/D/src/fadd.d_b12-01.S",
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"rv32i_m/D/src/fadd.d_b13-01.S",
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"rv32i_m/D/src/fadd.d_b2-01.S",
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"rv32i_m/D/src/fadd.d_b3-01.S",
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"rv32i_m/D/src/fadd.d_b4-01.S",
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"rv32i_m/D/src/fadd.d_b5-01.S",
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"rv32i_m/D/src/fadd.d_b7-01.S",
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"rv32i_m/D/src/fadd.d_b8-01.S",
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"rv32i_m/D/src/fclass.d_b1-01.S",
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"rv64i_m/D/src/fadd.d_b10-01.S",
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"rv64i_m/D/src/fadd.d_b1-01.S",
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"rv64i_m/D/src/fadd.d_b11-01.S",
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"rv64i_m/D/src/fadd.d_b12-01.S",
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"rv64i_m/D/src/fadd.d_b13-01.S",
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"rv64i_m/D/src/fadd.d_b2-01.S",
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"rv64i_m/D/src/fadd.d_b3-01.S",
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"rv64i_m/D/src/fadd.d_b4-01.S",
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"rv64i_m/D/src/fadd.d_b5-01.S",
|
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"rv64i_m/D/src/fadd.d_b7-01.S",
|
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"rv64i_m/D/src/fadd.d_b8-01.S",
|
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"rv64i_m/D/src/fclass.d_b1-01.S",
|
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"rv64i_m/D/src/fcvt.d.l_b25-01.S",
|
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"rv64i_m/D/src/fcvt.d.l_b26-01.S",
|
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"rv64i_m/D/src/fcvt.d.lu_b25-01.S",
|
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"rv64i_m/D/src/fcvt.d.lu_b26-01.S",
|
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"rv32i_m/D/src/fcvt.d.s_b1-01.S",
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"rv32i_m/D/src/fcvt.d.s_b22-01.S",
|
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"rv32i_m/D/src/fcvt.d.s_b23-01.S",
|
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"rv32i_m/D/src/fcvt.d.s_b24-01.S",
|
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"rv32i_m/D/src/fcvt.d.s_b27-01.S",
|
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"rv32i_m/D/src/fcvt.d.s_b28-01.S",
|
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"rv32i_m/D/src/fcvt.d.s_b29-01.S",
|
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"rv32i_m/D/src/fcvt.d.w_b25-01.S",
|
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"rv32i_m/D/src/fcvt.d.w_b26-01.S",
|
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"rv32i_m/D/src/fcvt.d.wu_b25-01.S",
|
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"rv32i_m/D/src/fcvt.d.wu_b26-01.S",
|
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"rv64i_m/D/src/fcvt.d.s_b1-01.S",
|
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"rv64i_m/D/src/fcvt.d.s_b22-01.S",
|
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"rv64i_m/D/src/fcvt.d.s_b23-01.S",
|
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"rv64i_m/D/src/fcvt.d.s_b24-01.S",
|
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"rv64i_m/D/src/fcvt.d.s_b27-01.S",
|
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"rv64i_m/D/src/fcvt.d.s_b28-01.S",
|
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"rv64i_m/D/src/fcvt.d.s_b29-01.S",
|
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"rv64i_m/D/src/fcvt.d.w_b25-01.S",
|
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"rv64i_m/D/src/fcvt.d.w_b26-01.S",
|
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"rv64i_m/D/src/fcvt.d.wu_b25-01.S",
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"rv64i_m/D/src/fcvt.d.wu_b26-01.S",
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"rv64i_m/D/src/fcvt.l.d_b1-01.S",
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"rv64i_m/D/src/fcvt.l.d_b22-01.S",
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"rv64i_m/D/src/fcvt.l.d_b23-01.S",
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@ -1095,135 +1246,135 @@ string imperas32f[] = '{
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"rv64i_m/D/src/fcvt.lu.d_b27-01.S",
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"rv64i_m/D/src/fcvt.lu.d_b28-01.S",
|
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"rv64i_m/D/src/fcvt.lu.d_b29-01.S",
|
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"rv32i_m/D/src/fcvt.s.d_b1-01.S",
|
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"rv32i_m/D/src/fcvt.s.d_b22-01.S",
|
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"rv32i_m/D/src/fcvt.s.d_b23-01.S",
|
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"rv32i_m/D/src/fcvt.s.d_b24-01.S",
|
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"rv32i_m/D/src/fcvt.s.d_b27-01.S",
|
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"rv32i_m/D/src/fcvt.s.d_b28-01.S",
|
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"rv32i_m/D/src/fcvt.s.d_b29-01.S",
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"rv32i_m/D/src/fcvt.w.d_b1-01.S",
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"rv32i_m/D/src/fcvt.w.d_b22-01.S",
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"rv32i_m/D/src/fcvt.w.d_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b29-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b29-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b1-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b20-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b2-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b21-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b3-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b4-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b5-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b6-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b7-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b8-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b9-01.S",
|
||||
"rv32i_m/D/src/feq.d_b1-01.S",
|
||||
"rv32i_m/D/src/feq.d_b19-01.S",
|
||||
"rv32i_m/D/src/fle.d_b1-01.S",
|
||||
"rv32i_m/D/src/fle.d_b19-01.S",
|
||||
"rv32i_m/D/src/flt.d_b1-01.S",
|
||||
"rv32i_m/D/src/flt.d_b19-01.S",
|
||||
// "rv32i_m/D/src/fld-align-01.S", //missing right now from top of tree, should be returned when it comes back
|
||||
// "rv32i_m/D/src/fsd-align-01.S", //https://github.com/riscv-non-isa/riscv-arch-test/issues/266
|
||||
"rv32i_m/D/src/fmadd.d_b14-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b16-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b17-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b18-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmax.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmax.d_b19-01.S",
|
||||
"rv32i_m/D/src/fmin.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmin.d_b19-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b14-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b16-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b17-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b18-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b9-01.S",
|
||||
"rv32i_m/D/src/fmv.d.x_b25-01.S",
|
||||
"rv32i_m/D/src/fmv.d.x_b26-01.S",
|
||||
"rv32i_m/D/src/fmv.x.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmv.x.d_b22-01.S",
|
||||
"rv32i_m/D/src/fmv.x.d_b23-01.S",
|
||||
"rv32i_m/D/src/fmv.x.d_b24-01.S",
|
||||
"rv32i_m/D/src/fmv.x.d_b27-01.S",
|
||||
"rv32i_m/D/src/fmv.x.d_b28-01.S",
|
||||
"rv32i_m/D/src/fmv.x.d_b29-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b14-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b16-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b17-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b18-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b2-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b3-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b4-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b5-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b6-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b7-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b8-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b14-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b16-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b17-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b18-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b6-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b8-01.S",
|
||||
"rv32i_m/D/src/fsgnj.d_b1-01.S",
|
||||
"rv32i_m/D/src/fsgnjn.d_b1-01.S",
|
||||
"rv32i_m/D/src/fsgnjx.d_b1-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b1-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b20-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b2-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b3-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b4-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b5-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b7-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b8-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b9-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b10-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b1-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b11-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b12-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b13-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b8-01.S"
|
||||
"rv64i_m/D/src/fcvt.s.d_b1-01.S",
|
||||
"rv64i_m/D/src/fcvt.s.d_b22-01.S",
|
||||
"rv64i_m/D/src/fcvt.s.d_b23-01.S",
|
||||
"rv64i_m/D/src/fcvt.s.d_b24-01.S",
|
||||
"rv64i_m/D/src/fcvt.s.d_b27-01.S",
|
||||
"rv64i_m/D/src/fcvt.s.d_b28-01.S",
|
||||
"rv64i_m/D/src/fcvt.s.d_b29-01.S",
|
||||
"rv64i_m/D/src/fcvt.w.d_b1-01.S",
|
||||
"rv64i_m/D/src/fcvt.w.d_b22-01.S",
|
||||
"rv64i_m/D/src/fcvt.w.d_b23-01.S",
|
||||
"rv64i_m/D/src/fcvt.w.d_b24-01.S",
|
||||
"rv64i_m/D/src/fcvt.w.d_b27-01.S",
|
||||
"rv64i_m/D/src/fcvt.w.d_b28-01.S",
|
||||
"rv64i_m/D/src/fcvt.w.d_b29-01.S",
|
||||
"rv64i_m/D/src/fcvt.wu.d_b1-01.S",
|
||||
"rv64i_m/D/src/fcvt.wu.d_b22-01.S",
|
||||
"rv64i_m/D/src/fcvt.wu.d_b23-01.S",
|
||||
"rv64i_m/D/src/fcvt.wu.d_b24-01.S",
|
||||
"rv64i_m/D/src/fcvt.wu.d_b27-01.S",
|
||||
"rv64i_m/D/src/fcvt.wu.d_b28-01.S",
|
||||
"rv64i_m/D/src/fcvt.wu.d_b29-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b1-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b20-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b2-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b21-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b3-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b4-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b5-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b6-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b7-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b8-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b9-01.S",
|
||||
"rv64i_m/D/src/feq.d_b1-01.S",
|
||||
"rv64i_m/D/src/feq.d_b19-01.S",
|
||||
"rv64i_m/D/src/fle.d_b1-01.S",
|
||||
"rv64i_m/D/src/fle.d_b19-01.S",
|
||||
"rv64i_m/D/src/flt.d_b1-01.S",
|
||||
"rv64i_m/D/src/flt.d_b19-01.S",
|
||||
// "rv64i_m/D/src/fld-align-01.S", //missing right now from top of tree, should be returned when it comes back
|
||||
// "rv64i_m/D/src/fsd-align-01.S", //https://github.com/riscv-non-isa/riscv-arch-test/issues/266
|
||||
"rv64i_m/D/src/fmadd.d_b14-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b16-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b17-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b18-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b2-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b3-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b4-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b5-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b6-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b7-01.S",
|
||||
"rv64i_m/D/src/fmadd.d_b8-01.S",
|
||||
"rv64i_m/D/src/fmax.d_b1-01.S",
|
||||
"rv64i_m/D/src/fmax.d_b19-01.S",
|
||||
"rv64i_m/D/src/fmin.d_b1-01.S",
|
||||
"rv64i_m/D/src/fmin.d_b19-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b14-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b16-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b17-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b18-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b2-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b3-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b4-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b5-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b6-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b7-01.S",
|
||||
"rv64i_m/D/src/fmsub.d_b8-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b1-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b2-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b3-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b4-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b5-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b6-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b7-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b8-01.S",
|
||||
"rv64i_m/D/src/fmul.d_b9-01.S",
|
||||
"rv64i_m/D/src/fmv.d.x_b25-01.S",
|
||||
"rv64i_m/D/src/fmv.d.x_b26-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b1-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b22-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b23-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b24-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b27-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b28-01.S",
|
||||
"rv64i_m/D/src/fmv.x.d_b29-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b14-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b16-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b17-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b18-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b2-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b3-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b4-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b5-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b6-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b7-01.S",
|
||||
"rv64i_m/D/src/fnmadd.d_b8-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b14-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b16-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b17-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b18-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b2-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b3-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b4-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b5-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b6-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b7-01.S",
|
||||
"rv64i_m/D/src/fnmsub.d_b8-01.S",
|
||||
"rv64i_m/D/src/fsgnj.d_b1-01.S",
|
||||
"rv64i_m/D/src/fsgnjn.d_b1-01.S",
|
||||
"rv64i_m/D/src/fsgnjx.d_b1-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b1-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b20-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b2-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b3-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b4-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b5-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b7-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b8-01.S",
|
||||
// "rv64i_m/D/src/fsqrt.d_b9-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b10-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b1-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b11-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b12-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b13-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b2-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b3-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b4-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b5-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b7-01.S",
|
||||
"rv64i_m/D/src/fssub.d_b8-01.S"
|
||||
};
|
||||
|
||||
string arch32priv[] = '{
|
||||
@ -1408,6 +1559,153 @@ string imperas32f[] = '{
|
||||
// "rv32i_m/F/src/fsw-align-01.S"
|
||||
};
|
||||
|
||||
string arch32d[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/D/src/fadd.d_b10-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b1-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b11-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b12-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b13-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b2-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b3-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b4-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b5-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b7-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b8-01.S",
|
||||
"rv32i_m/D/src/fclass.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b29-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.w_b25-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.w_b26-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.wu_b25-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.wu_b26-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b29-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b29-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b29-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b1-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b20-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b2-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b21-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b3-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b4-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b5-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b6-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b7-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b8-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b9-01.S",
|
||||
"rv32i_m/D/src/feq.d_b1-01.S",
|
||||
"rv32i_m/D/src/feq.d_b19-01.S",
|
||||
"rv32i_m/D/src/fle.d_b1-01.S",
|
||||
"rv32i_m/D/src/fle.d_b19-01.S",
|
||||
"rv32i_m/D/src/flt.d_b1-01.S",
|
||||
"rv32i_m/D/src/flt.d_b19-01.S",
|
||||
// "rv32i_m/D/src/fld-align-01.S", //missing right now from top of tree, should be returned when it comes back
|
||||
// "rv32i_m/D/src/fsd-align-01.S", //https://github.com/riscv-non-isa/riscv-arch-test/issues/266
|
||||
"rv32i_m/D/src/fmadd.d_b14-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b16-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b17-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b18-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmax.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmax.d_b19-01.S",
|
||||
"rv32i_m/D/src/fmin.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmin.d_b19-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b14-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b16-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b17-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b18-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b9-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b14-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b16-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b17-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b18-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b2-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b3-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b4-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b5-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b6-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b7-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b8-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b14-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b16-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b17-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b18-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b6-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b8-01.S",
|
||||
"rv32i_m/D/src/fsgnj.d_b1-01.S",
|
||||
"rv32i_m/D/src/fsgnjn.d_b1-01.S",
|
||||
"rv32i_m/D/src/fsgnjx.d_b1-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b1-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b20-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b2-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b3-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b4-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b5-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b7-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b8-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b9-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b10-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b1-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b11-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b12-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b13-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b8-01.S"
|
||||
};
|
||||
|
||||
|
||||
string arch32c[] = '{
|
||||
`RISCVARCHTEST,
|
||||
|
||||
@ -8,8 +8,8 @@ wally_workdir = $(work)/wally-riscv-arch-test
|
||||
current_dir = $(shell pwd)
|
||||
#XLEN ?= 64
|
||||
|
||||
#all: root fsd_fld_tempfix arch32 wally32 wally32e arch64 wally64
|
||||
all: root fsd_fld_tempfix arch32
|
||||
all: root fsd_fld_tempfix arch32 wally32 wally32e arch64 wally64
|
||||
#all: root fsd_fld_tempfix arch64
|
||||
|
||||
root:
|
||||
mkdir -p $(work_dir)
|
||||
@ -33,6 +33,8 @@ arch32:
|
||||
arch64:
|
||||
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
|
||||
rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"
|
||||
# Also copy F and D tests to RV64
|
||||
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"
|
||||
|
||||
wally32:
|
||||
riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
|
||||
|
||||
@ -127,4 +127,6 @@ class sail_cSim(pluginTemplate):
|
||||
execute+=coverage_cmd
|
||||
|
||||
make.add_target(execute)
|
||||
make.execute_all(self.work_dir)
|
||||
# make.execute_all(self.work_dir)
|
||||
# DH 7/26/22 increase timeout so sim will finish on slow machines
|
||||
make.execute_all(self.work_dir, timeout = 600)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user