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Cause simplification

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This commit is contained in:
David Harris 2022-05-12 23:27:02 +00:00
parent 87dadc8208
commit 2d27d20db9
2 changed files with 3 additions and 3 deletions
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2
pipelined/src/privileged/privileged.sv
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@ -104,7 +104,7 @@ module privileged (
// track the current privilege level // track the current privilege level
/////////////////////////////////////////// ///////////////////////////////////////////
privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .CauseM, privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .InterruptM, .CauseM,
.MEDELEG_REGW, .MIDELEG_REGW, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); .MEDELEG_REGW, .MIDELEG_REGW, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
/////////////////////////////////////////// ///////////////////////////////////////////

4
pipelined/src/privileged/privmode.sv
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@ -33,7 +33,7 @@
module privmode ( module privmode (
input logic clk, reset, input logic clk, reset,
input logic StallW, TrapM, mretM, sretM, input logic StallW, TrapM, mretM, sretM, InterruptM,
input logic [`XLEN-1:0] CauseM, MEDELEG_REGW, input logic [`XLEN-1:0] CauseM, MEDELEG_REGW,
input logic [11:0] MIDELEG_REGW, input logic [11:0] MIDELEG_REGW,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
@ -45,7 +45,7 @@ module privmode (
logic md; logic md;
// get bits of DELEG registers based on CAUSE // get bits of DELEG registers based on CAUSE
assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
// PrivilegeMode FSM // PrivilegeMode FSM
always_comb begin always_comb begin