diff --git a/.gitignore b/.gitignore index b745e3c63..047e9ed7a 100644 --- a/.gitignore +++ b/.gitignore @@ -51,4 +51,5 @@ fpga/generator/*.jou examples/asm/sumtest/sumtest examples/asm/example/example examples/C/sum/sum +examples/C/fir/fir diff --git a/addins/soc_flow b/addins/soc_flow index 60ca3dac1..ba0cbc1d9 160000 --- a/addins/soc_flow +++ b/addins/soc_flow @@ -1 +1 @@ -Subproject commit 60ca3dac1ae096740d3a6d19a5885f5f056ddb04 +Subproject commit ba0cbc1d90e0aec296aed42fa87b20b9a575b5cf diff --git a/examples/C/fir/Makefile b/examples/C/fir/Makefile index b1f4738cc..c27e423a5 100644 --- a/examples/C/fir/Makefile +++ b/examples/C/fir/Makefile @@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET) spike $(TARGET) $(TARGET): $(TARGET).c Makefile - riscv64-unknown-elf-gcc -o $(TARGET) -g -O\ + riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\ -march=rv64gc -mabi=lp64d -mcmodel=medany \ -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ -T../common/test.ld -I../common \ diff --git a/examples/C/fir/fir b/examples/C/fir/fir index f395b2e7e..4266f84b9 100755 Binary files a/examples/C/fir/fir and b/examples/C/fir/fir differ diff --git a/pipelined/config/rv32etim/wally-config.vh b/pipelined/config/rv32etim/wally-config.vh index 450506701..58e31d2cd 100644 --- a/pipelined/config/rv32etim/wally-config.vh +++ b/pipelined/config/rv32etim/wally-config.vh @@ -86,10 +86,10 @@ // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h00000FFF +`define BOOTROM_RANGE 34'h000000FF `define RAM_SUPPORTED 1'b1 `define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h0000FFFF +`define RAM_RANGE 34'h000003FF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF @@ -129,6 +129,6 @@ `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" -`define BPRED_ENABLED 1 +`define BPRED_ENABLED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/fpu-testfloat/FMA/tbgen/tb.sv b/pipelined/fpu-testfloat/FMA/tbgen/tb.sv index 621429aa4..57c4e2ff0 100644 --- a/pipelined/fpu-testfloat/FMA/tbgen/tb.sv +++ b/pipelined/fpu-testfloat/FMA/tbgen/tb.sv @@ -129,11 +129,11 @@ assign FmtE = 1'b1; assign BiasE = 13'h3ff; -assign wnan = FmtE ? &FMAResM[`FLEN-2:`NF] && |FMAResM[`NF-1:0] : &FMAResM[30:23] && |FMAResM[22:0]; -// assign XNaNE = FmtE ? &X[62:52] && |X[51:0] : &X[62:55] && |X[54:32]; -// assign YNaNE = FmtE ? &Y[62:52] && |Y[51:0] : &Y[62:55] && |Y[54:32]; -// assign ZNaNE = FmtE ? &Z[62:52] && |Z[51:0] : &Z[62:55] && |Z[54:32]; -assign ansnan = FmtE ? &ans[`FLEN-2:`NF] && |ans[`NF-1:0] : &ans[30:23] && |ans[22:0]; +assign wnan = FmtE ? &FMAResM[`FLEN-2:`NF] & |FMAResM[`NF-1:0] : &FMAResM[30:23] & |FMAResM[22:0]; +// assign XNaNE = FmtE ? &X[62:52] & |X[51:0] : &X[62:55] & |X[54:32]; +// assign YNaNE = FmtE ? &Y[62:52] & |Y[51:0] : &Y[62:55] & |Y[54:32]; +// assign ZNaNE = FmtE ? &Z[62:52] & |Z[51:0] : &Z[62:55] & |Z[54:32]; +assign ansnan = FmtE ? &ans[`FLEN-2:`NF] & |ans[`NF-1:0] : &ans[30:23] & |ans[22:0]; // instantiate device under test logic [3*`NF+5:0] SumE, SumM; @@ -179,9 +179,9 @@ always @(posedge clk) // check results on falling edge of clk always @(negedge clk) begin - if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] == {XExpE,1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] == {YExpE,1'b1,Y[`NF-2:0]})) || (ZNaNE && (FMAResM[`FLEN-2:0] == {ZExpE,1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] == ans[`FLEN-2:0]))))) begin + if((FmtE==1'b1) & (FMAFlgM != flags[4:0] | (!wnan & (FMAResM != ans)) | (wnan & ansnan & ~((XNaNE & (FMAResM[`FLEN-2:0] == {XExpE,1'b1,X[`NF-2:0]})) | (YNaNE & (FMAResM[`FLEN-2:0] == {YExpE,1'b1,Y[`NF-2:0]})) | (ZNaNE & (FMAResM[`FLEN-2:0] == {ZExpE,1'b1,Z[`NF-2:0]})) | (FMAResM[`FLEN-2:0] == ans[`FLEN-2:0]))))) begin // fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w"); - // if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (FMAResM != ans))) begin + // if((FmtE==1'b1) & (FMAFlgM != flags[4:0] | (FMAResM != ans))) begin $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero "); if(XDenormE) $display( "xdenorm "); @@ -190,35 +190,35 @@ always @(posedge clk) if(FMAFlgM[4] != 0) $display( "invld "); if(FMAFlgM[2] != 0) $display( "ovrflw "); if(FMAFlgM[1] != 0) $display( "unflw "); - if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} && FMAResM[`NF-1:0] == 0) $display( "FMAResM=-inf "); - if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} && FMAResM[`NF-1:0] == 0) $display( "FMAResM=+inf "); - if(FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} && FMAResM[`NF-1:0] != 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); - if(FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} && FMAResM[`NF-1:0] != 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); - if(ans[`FLEN] && ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] == 0) $display( "ans=-inf "); - if(~ans[`FLEN] && ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] == 0) $display( "ans=+inf "); - if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ~ans[`NF-1]) $display( "ans=sigNaN "); - if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ans[`NF-1]) $display( "ans=qutNaN "); + if(FMAResM[`FLEN] & FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} & FMAResM[`NF-1:0] == 0) $display( "FMAResM=-inf "); + if(~FMAResM[`FLEN] & FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} & FMAResM[`NF-1:0] == 0) $display( "FMAResM=+inf "); + if(FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} & FMAResM[`NF-1:0] != 0 & ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN "); + if(FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} & FMAResM[`NF-1:0] != 0 & FMAResM[`NF-1]) $display( "FMAResM=qutNaN "); + if(ans[`FLEN] & ans[`FLEN-2:`NF] == {`NE{1'b1}} & ans[`NF-1:0] == 0) $display( "ans=-inf "); + if(~ans[`FLEN] & ans[`FLEN-2:`NF] == {`NE{1'b1}} & ans[`NF-1:0] == 0) $display( "ans=+inf "); + if(ans[`FLEN-2:`NF] == {`NE{1'b1}} & ans[`NF-1:0] != 0 & ~ans[`NF-1]) $display( "ans=sigNaN "); + if(ans[`FLEN-2:`NF] == {`NE{1'b1}} & ans[`NF-1:0] != 0 & ans[`NF-1]) $display( "ans=qutNaN "); errors = errors + 1; //if (errors == 10) $stop; end - if((FmtE==1'b0)&(FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[30:0] == {X[30:23],1'b1,X[21:0]})) || (YNaNE && (FMAResM[30:0] == {Y[30:23],1'b1,Y[21:0]})) || (ZNaNE && (FMAResM[30:0] == {Z[30:23],1'b1,Z[21:0]})) || (FMAResM[30:0] == ans[30:0]))) ))) begin + if((FmtE==1'b0)&(FMAFlgM != flags[4:0] | (!wnan & (FMAResM != ans)) | (wnan & ansnan & ~(((XNaNE & (FMAResM[30:0] == {X[30:23],1'b1,X[21:0]})) | (YNaNE & (FMAResM[30:0] == {Y[30:23],1'b1,Y[21:0]})) | (ZNaNE & (FMAResM[30:0] == {Z[30:23],1'b1,Z[21:0]})) | (FMAResM[30:0] == ans[30:0]))) ))) begin $display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags); if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero "); - if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm "); - if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm "); - if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm "); + if(~(|X[30:23]) & |X[22:0]) $display( "xdenorm "); + if(~(|Y[30:23]) & |Y[22:0]) $display( "ydenorm "); + if(~(|Z[30:23]) & |Z[22:0]) $display( "zdenorm "); if(FMAFlgM[4] != 0) $display( "invld "); if(FMAFlgM[2] != 0) $display( "ovrflw "); if(FMAFlgM[1] != 0) $display( "unflw "); if(FMAResM == 64'hFF80000000000000) $display( "FMAResM=-inf "); if(FMAResM == 64'h7F80000000000000) $display( "FMAResM=+inf "); - if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN "); - if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN "); + if(&FMAResM[30:23] & |FMAResM[22:0] & ~FMAResM[22]) $display( "FMAResM=sigNaN "); + if(&FMAResM[30:23] & |FMAResM[22:0] & FMAResM[22] ) $display( "FMAResM=qutNaN "); if(ans == 64'hFF80000000000000) $display( "ans=-inf "); if(ans == 64'h7F80000000000000) $display( "ans=+inf "); - if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN "); - if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN "); + if(&ans[30:23] & |ans[22:0] & ~ans[22] ) $display( "ans=sigNaN "); + if(&ans[30:23] & |ans[22:0] & ans[22]) $display( "ans=qutNaN "); errors = errors + 1; if (errors == 10) $stop; diff --git a/pipelined/src/fpu/cvtfp.sv b/pipelined/src/fpu/cvtfp.sv index 0b91b82e4..95c0d1799 100644 --- a/pipelined/src/fpu/cvtfp.sv +++ b/pipelined/src/fpu/cvtfp.sv @@ -40,7 +40,7 @@ module cvtfp ( logic [8:0] i,NormCnt; always_comb begin i = 0; - while (~XManE[52-i] && i <= 52) i = i+1; // search for leading one + while (~XManE[52-i] & i <= 52) i = i+1; // search for leading one NormCnt = i; end diff --git a/pipelined/src/fpu/faddcvt.sv b/pipelined/src/fpu/faddcvt.sv index 5737b463d..e5dddb7e9 100755 --- a/pipelined/src/fpu/faddcvt.sv +++ b/pipelined/src/fpu/faddcvt.sv @@ -187,12 +187,12 @@ module fpuaddcvt1 ( logic [8:0] j; always_comb begin i = 0; - while (~mantissaA[52-i] && $unsigned(i) <= $unsigned(52)) i = i+1; // search for leading one + while (~mantissaA[52-i] & $unsigned(i) <= $unsigned(52)) i = i+1; // search for leading one ZP_mantissaA = i; end always_comb begin j = 0; - while (~mantissaB[52-j] && $unsigned(j) <= $unsigned(52)) j = j+1; // search for leading one + while (~mantissaB[52-j] & $unsigned(j) <= $unsigned(52)) j = j+1; // search for leading one ZP_mantissaB = j; end diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index e238560ff..3e89afde2 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -85,7 +85,7 @@ module fcvt ( logic [8:0] i; always_comb begin i = 0; - while (~PosInt[64-1-i] && i < `XLEN) i = i+1; // search for leading one + while (~PosInt[64-1-i] & i < `XLEN) i = i+1; // search for leading one LZResP = i[5:0]+1; // compute shift count end diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 368d02c47..3ce4495ce 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -396,7 +396,7 @@ module lzc( logic [8:0] i; always_comb begin i = 0; - while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one + while (~f[3*`NF+6-i] & $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one NormCntE = i; end endmodule @@ -768,7 +768,7 @@ module fmaflags( // 3) 0 * Inf assign SigNaN = XSNaNM | YSNaNM | ZSNaNM; - assign Invalid = SigNaN | ((XInfM || YInfM) & ZInfM & (PSgnM ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM); + assign Invalid = SigNaN | ((XInfM | YInfM) & ZInfM & (PSgnM ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM); // Set Overflow flag if the number is too big to be represented // - Don't set the overflow flag if an overflowed result isn't outputed diff --git a/pipelined/src/fpu/fsm_fpdiv_pipe.sv b/pipelined/src/fpu/fsm_fpdiv_pipe.sv index afef96be9..33d270b89 100755 --- a/pipelined/src/fpu/fsm_fpdiv_pipe.sv +++ b/pipelined/src/fpu/fsm_fpdiv_pipe.sv @@ -129,7 +129,7 @@ module fsm_fpdiv_pipe ( end // if (start==1'b0) S65: begin - if (op_type==1'b0 && P==1'b0) + if (op_type==1'b0 & P==1'b0) begin done = 1'b0; divBusy = 1'b1; @@ -146,7 +146,7 @@ module fsm_fpdiv_pipe ( sel_muxr = 1'b0; next_state = S1; end - else if (op_type==1'b0 && P==1'b1) + else if (op_type==1'b0 & P==1'b1) begin done = 1'b0; divBusy = 1'b1; @@ -163,7 +163,7 @@ module fsm_fpdiv_pipe ( sel_muxr = 1'b0; next_state = S36; end - else if (op_type==1'b1 && P==1'b0) + else if (op_type==1'b1 & P==1'b0) begin done = 1'b0; divBusy = 1'b1; @@ -180,7 +180,7 @@ module fsm_fpdiv_pipe ( sel_muxr = 1'b0; next_state = S15; end - else if (op_type==1'b1 && P==1'b1) + else if (op_type==1'b1 & P==1'b1) begin done = 1'b0; divBusy = 1'b1; diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 7fde50036..c48e3d2e7 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -86,7 +86,7 @@ module csrc #(parameter // Determine when to increment each counter assign CounterEvent[0] = 1'b1; // MCYCLE always increments - assign CounterEvent[1] = 1'b0; // Counter 0 doesn't exist + assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist assign CounterEvent[2] = InstrValidNotFlushedM; if(`QEMU) begin: cevent // No other performance counters in QEMU assign CounterEvent[`COUNTERS-1:3] = 0; diff --git a/pipelined/testbench/sdc/sdModel.sv b/pipelined/testbench/sdc/sdModel.sv index 1e36c23e2..f2a5127d8 100644 --- a/pipelined/testbench/sdc/sdModel.sv +++ b/pipelined/testbench/sdc/sdModel.sv @@ -361,7 +361,7 @@ module sdModel next_state = READ_CMD; end ANALYZE_CMD: begin - if ((ValidCmd ) && (outDelayCnt >= `outDelay )) // outDelayCnt >= 4 (NCR) + if ((ValidCmd ) & (outDelayCnt >= `outDelay )) // outDelayCnt >= 4 (NCR) next_state = SEND_CMD; else if (inValidCmd) next_state = IDLE; @@ -387,7 +387,7 @@ module sdModel DATA_IDLE: begin if ((CardStatus[12:9]==`RCV) | (mult_write == 1'b1) ) next_datastate = READ_WAITS; - else if ((CardStatus[12:9]==`DATAS )|| (mult_read == 1'b1) ) + else if ((CardStatus[12:9]==`DATAS )| (mult_read == 1'b1) ) next_datastate = WRITE_DATA; else next_datastate = DATA_IDLE; @@ -551,7 +551,7 @@ module sdModel ResetCard; end 2 : begin //ALL_SEND_CARD_ID (CID) - if (lastCMD != 41 && outDelayCnt==0) begin + if (lastCMD != 41 & outDelayCnt==0) begin $fdisplay(sdModel_file_desc, "**Error in sequence, ACMD 41 should precede 2 in Start-up state") ; //$display(sdModel_file_desc, "**Error in sequence, ACMD 41 should precede 2 in Start-up state") ; CardStatus[3]<=1; // AKE_SEQ_ERROR = ERROR in sequence of authentication process @@ -561,7 +561,7 @@ module sdModel CardStatus[12:9] <=2; end 3 : begin //SEND_RELATIVE_CARD_ADDRESS (RCA) - if (lastCMD != 2 && outDelayCnt==0 ) begin + if (lastCMD != 2 & outDelayCnt==0 ) begin $fdisplay(sdModel_file_desc, "**Error in sequence, CMD 2 should precede 3 in Start-up state") ; //$display(sdModel_file_desc, "**Error in sequence, CMD 2 should precede 3 in Start-up state") ; CardStatus[3]<=1; // AKE_SEQ_ERROR = ERROR in sequence of authentication process @@ -573,7 +573,7 @@ module sdModel cardIdentificationState<=0; end 6 : begin - if (lastCMD == 55 && outDelayCnt==0) begin //ACMD6 - SET_BUS_WIDTH + if (lastCMD == 55 & outDelayCnt==0) begin //ACMD6 - SET_BUS_WIDTH if (inCmd[9:8] == 2'b10) begin BusWidth <=4; $display(sdModel_file_desc, "**BUS WIDTH 4 ") ; @@ -627,7 +627,7 @@ module sdModel end 9 : begin // SEND_CARD_SPECIFIC_DATA (CSD) - if (lastCMD != 41 && outDelayCnt==0) begin + if (lastCMD != 41 & outDelayCnt==0) begin $fdisplay(sdModel_file_desc, "**Error in sequence, ACMD 41 should precede 9 in Start-up state") ; //$display(sdModel_file_desc, "**Error in sequence, ACMD 41 should precede 9 in Start-up state") ; CardStatus[3]<=1; // AKE_SEQ_ERROR = ERROR in sequence of authentication process @@ -743,7 +743,7 @@ module sdModel 41 : // CMD41 - SD_SEND_OCR begin if (cardIdentificationState) begin - if (lastCMD != 55 && outDelayCnt==0) begin // CMD41 - Reserved/Invalid + if (lastCMD != 55 & outDelayCnt==0) begin // CMD41 - Reserved/Invalid $fdisplay(sdModel_file_desc, "**Error in sequence, CMD 55 should precede 41 in Start-up state") ; $display( "**Error in sequence, CMD 55 should precede 41 in Start-up state") ; CardStatus[3]<=1; // AKE_SEQ_ERROR = ERROR in sequence of authentication process @@ -755,7 +755,7 @@ module sdModel CardStatus[5] <=0; // not expecting next command to be ACMD if (Busy==1) CardStatus[12:9] <=1; // READY - end // else: !if(lastCMD != 55 && outDelayCnt==0) + end // else: !if(lastCMD != 55 & outDelayCnt==0) end // if (cardIdentificationState) end // case: 41 endcase // case (inCmd[45:40]) @@ -799,7 +799,7 @@ module sdModel else cmdOut<=1; - if ((cmdWrite>0) && (cmdWrite < response_S-8)) begin + if ((cmdWrite>0) & (cmdWrite < response_S-8)) begin cmdOut<=response_CMD[135-cmdWrite]; crcIn<=response_CMD[134-cmdWrite]; if (cmdWrite >= response_S-9) @@ -948,7 +948,7 @@ module sdModel data_send_index<=1; // Next nibble is lower nibble end - else if ( (transf_cnt>=2) && (transf_cnt<=BLOCK_WIDTH -`CRC_OFF )) begin // if (2 <= transf_cnt <= 1025) + else if ( (transf_cnt>=2) & (transf_cnt<=BLOCK_WIDTH -`CRC_OFF )) begin // if (2 <= transf_cnt <= 1025) data_send_index<=~data_send_index; //toggle if (!data_send_index) begin //upper nibble if (BLOCK_WIDTH == 11'd1044) begin @@ -987,7 +987,7 @@ module sdModel if ( transf_cnt >=BLOCK_WIDTH-`CRC_OFF ) begin // if (trans_cnt >= 1025) crcDat_en<=0; // Disable CRC16 Generators end - end // if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) + end // if ( (transf_cnt>=2) & (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) else if (transf_cnt>BLOCK_WIDTH-`CRC_OFF & crc_c!=0) begin // if ((transf_cnt > 1025) and (crc_c /= 0)) datOut<= last_din; // if sent all data bitsbut not crc16 bits yet @@ -1004,7 +1004,7 @@ module sdModel else if (transf_cnt==BLOCK_WIDTH-2) begin // if (transf_cnt = 1042) Last CRC16 bit is 1041 datOut<=4'b1111; // send end bits end - else if ((transf_cnt !=0) && (crc_c == 0 ))begin // if sent data bits and crc_c points past last bit of CRC + else if ((transf_cnt !=0) & (crc_c == 0 ))begin // if sent data bits and crc_c points past last bit of CRC oeDat<=0; // disable output on DAT bus CardStatus[12:9] <= `TRAN; // put card in transfer state end @@ -1026,14 +1026,14 @@ module sdModel else if(flash_write_cnt == 2) datOut[0]<=0; - else if ((flash_write_cnt > 2) && (flash_write_cnt < 7)) begin + else if ((flash_write_cnt > 2) & (flash_write_cnt < 7)) begin if (crc_ok) datOut[0] <=okcrctoken[6-flash_write_cnt]; else datOut[0] <= invalidcrctoken[6-flash_write_cnt]; end - else if ((flash_write_cnt >= 7) && (flash_write_cnt < 264)) begin + else if ((flash_write_cnt >= 7) & (flash_write_cnt < 264)) begin datOut[0]<=0; flash_blockwrite_cnt<=flash_blockwrite_cnt+2; @@ -1045,7 +1045,7 @@ module sdModel datOut<=1; InbuffStatus<=0; CardStatus[12:9] <= `TRAN; - end // else: !if((flash_write_cnt >= 7) && (flash_write_cnt < 264)) + end // else: !if((flash_write_cnt >= 7) & (flash_write_cnt < 264)) end // case: WRITE_FLASH endcase // case (dataState) end // always @ (negedge sdClk) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index b31140dd9..48cd4e891 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -379,7 +379,7 @@ module testbench; //$display("len = %d", line``STAGE.len()); \ for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \ //$display("char = %s", line``STAGE[index]); \ - if (line``STAGE[index``STAGE] == " " || line``STAGE[index``STAGE] == "\n") begin \ + if (line``STAGE[index``STAGE] == " " | line``STAGE[index``STAGE] == "\n") begin \ EndIndex``STAGE = index``STAGE; \ ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \ //$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \ @@ -412,7 +412,7 @@ module testbench; // parse CSRs, because there are 1 or more CSRs after the CSR token \ // we check if the CSR token or the number of CSRs is greater than 0. \ // if so then we want to parse for a CSR. \ - end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" || NumCSR``STAGE > 0) begin \ + end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" | NumCSR``STAGE > 0) begin \ if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR") begin \ // all additional CSR's won't have this token. \ MarkerIndex``STAGE++; \ @@ -467,7 +467,7 @@ module testbench; // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); - if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) || ~dut.core.ieu.c.InstrValidM) begin + if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) | ~dut.core.ieu.c.InstrValidM) begin RequestDelayedMIP <= 1; $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); end else begin // update MIP immediately @@ -584,10 +584,10 @@ module testbench; if (MemOpW.substr(0,2) == "Mem") begin if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) - if(MemOpW == "MemR" || MemOpW == "MemRW") begin + if(MemOpW == "MemR" | MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(MemOpW == "MemW" || MemOpW == "MemRW") begin + end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) end @@ -680,7 +680,7 @@ module testbench; PTE = dut.uncore.ram.ram.RAM[PAdr >> 3]; PTE_R = PTE[1]; PTE_X = PTE[3]; - if (PTE_R || PTE_X) begin + if (PTE_R | PTE_X) begin // Leaf page found break; end else begin