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Fixed batch mode regression test to work with hpmc loggic.

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Added logic to exclude the embench warmups from preformance counters.
This commit is contained in:
Ross Thompson 2023-03-03 14:59:20 -06:00
parent 1c381b0546
commit 2d0512936b
2 changed files with 25 additions and 9 deletions
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4
sim/wally-batch.do
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@ -81,11 +81,11 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
#vsim -coverage -lib work_$2 workopt_$2 #vsim -coverage -lib work_$2 workopt_$2
do wave.do
# power add generates the logging necessary for said generation. # power add generates the logging necessary for said generation.
# power add -r /dut/core/* # power add -r /dut/core/*
run -all run -all

28
testbench/testbench.sv
View File

@ -406,7 +406,7 @@ logic [3:0] dummy;
logic StartSampleFirst; logic StartSampleFirst;
logic StartSampleDelayed; logic StartSampleDelayed;
logic StartSample; logic StartSample;
logic EndSample; logic EndSample, EndSampleFirst, EndSampleDelayed;
logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0]; logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
logic [`XLEN-1:0] FinalHPMCOUNTERH[`COUNTERS-1:0]; logic [`XLEN-1:0] FinalHPMCOUNTERH[`COUNTERS-1:0];
@ -436,11 +436,27 @@ logic [3:0] dummy;
"Exception", "Exception",
"Divide Cycles" "Divide Cycles"
}; };
assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
assign EndSample = DCacheFlushStart & ~DCacheFlushDone; if(TEST == "embench") begin
// embench runs warmup then runs start_trigger
// embench end with stop_trigger.
assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else begin
// default start condiction is reset
// default end condiction is end of test (DCacheFlushDone)
assign StartSampleFirst = InReset;
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
end
always @(negedge clk) begin always @(negedge clk) begin
if(StartSample) begin if(StartSample) begin
@ -465,7 +481,7 @@ logic [3:0] dummy;
// track the current function or global label // track the current function or global label
if (DEBUG == 1) begin : FunctionName if (DEBUG == 1 | (`PrintHPMCounters & `ZICOUNTERS_SUPPORTED)) begin : FunctionName
FunctionName FunctionName(.reset(reset), FunctionName FunctionName(.reset(reset),
.clk(clk), .clk(clk),
.ProgramAddrMapFile(ProgramAddrMapFile), .ProgramAddrMapFile(ProgramAddrMapFile),