From 2d0199a35475ad8254bdeb6c2825e6dbb5c593e8 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 24 Mar 2023 17:01:27 -0500 Subject: [PATCH] Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore --- fpga/constraints/constraints-vcu108.xdc | 48 ++++++----- fpga/src/fpgaTop.v | 66 ++++++++-------- src/uncore/uncore.sv | 8 +- src/wally/wallypipelinedsoc.sv | 6 +- tests/custom/boot/bios.s | 101 ++++++++++++++++++++++++ tests/custom/boot/boot.c | 19 ----- 6 files changed, 171 insertions(+), 77 deletions(-) create mode 100644 tests/custom/boot/bios.s diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index cbb70db92..8d59509be 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -3,7 +3,8 @@ # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] ##### GPI #### set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] @@ -16,7 +17,7 @@ set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] -set_max_delay -from [get_ports {GPI[*]}] 10.000 +set_max_delay -from [get_ports {GPI[*]}] 10.000n ##### GPO #### set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}] @@ -92,23 +93,32 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### -set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] -set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] -set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] -set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] -set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] -set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] -set_property PACKAGE_PIN BB16 [get_ports SDCCLK] -set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] -set_property PULLUP true [get_ports {SDCDat[3]}] -set_property PULLUP true [get_ports {SDCDat[2]}] -set_property PULLUP true [get_ports {SDCDat[1]}] -set_property PULLUP true [get_ports {SDCDat[0]}] -set_property PULLUP true [get_ports {SDCCmd}] + +# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] +# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] +# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] +# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] +# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] +# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] +# set_property PACKAGE_PIN BB16 [get_ports SDCCLK] +# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] +# set_property PULLUP true [get_ports {SDCDat[3]}] +# set_property PULLUP true [get_ports {SDCDat[2]}] +# set_property PULLUP true [get_ports {SDCDat[1]}] +# set_property PULLUP true [get_ports {SDCDat[0]}] +# set_property PULLUP true [get_ports {SDCCmd}] + +set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}] +set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}] +set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}] +set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}] +set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}] +set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}] +set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK] set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 13f61c03f..e2eb8441e 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -28,23 +28,24 @@ module fpgaTop (input default_250mhz_clk1_0_n, - input default_250mhz_clk1_0_p, - input reset, - input south_rst, + input default_250mhz_clk1_0_p, + input reset, + input south_rst, - input [3:0] GPI, + input [3:0] GPI, output [4:0] GPO, - input UARTSin, - output UARTSout, + input UARTSin, + output UARTSout, - inout [3:0] SDCDat, - output SDCCLK, - inout SDCCmd, + inout [3:0] SDCDat, + output SDCCLK, + inout SDCCmd, + input SDCCD, - output calib, - output cpu_reset, - output ahblite_resetn, + output calib, + output cpu_reset, + output ahblite_resetn, output [16 : 0] c0_ddr4_adr, output [1 : 0] c0_ddr4_ba, @@ -56,8 +57,8 @@ module fpgaTop inout [7 : 0] c0_ddr4_dqs_t, output [0 : 0] c0_ddr4_odt, output [0 : 0] c0_ddr4_bg, - output c0_ddr4_reset_n, - output c0_ddr4_act_n, + output c0_ddr4_reset_n, + output c0_ddr4_act_n, output [0 : 0] c0_ddr4_ck_c, output [0 : 0] c0_ddr4_ck_t ); @@ -188,6 +189,7 @@ module fpgaTop wire s00_axi_aclk; wire s00_axi_aresetn; + wire [3:0] s00_axi_awid; wire [31:0]s00_axi_awaddr; wire [7:0]s00_axi_awlen; wire [2:0]s00_axi_awsize; @@ -244,11 +246,9 @@ module fpgaTop wire s01_axi_wlast; wire s01_axi_wvalid; wire s01_axi_wready; - wire [3:0]m01_axi_bid; wire [1:0]s01_axi_bresp; wire s01_axi_bvalid; wire s01_axi_bready; - wire [3:0]m01_axi_bid; wire [31:0]s01_axi_araddr; wire [7:0]s01_axi_arlen; wire [2:0]s01_axi_arsize; @@ -260,7 +260,6 @@ module fpgaTop wire [3:0]s01_axi_arqos; // wire s01_axi_arvalid; wire s01_axi_arready; - wire [3:0]m01_axi_rid; wire [63:0]s01_axi_rdata; wire [1:0]s01_axi_rresp; wire s01_axi_rlast; @@ -376,7 +375,7 @@ module fpgaTop wire [3:0]m01_axi_awqos; wire m01_axi_awvalid; wire m01_axi_awready; - wire [31:0]m01_axi_wdata; + wire [63:0]m01_axi_wdata; wire [3:0]m01_axi_wstrb; wire m01_axi_wlast; wire m01_axi_wvalid; @@ -398,7 +397,7 @@ module fpgaTop wire m01_axi_arvalid; wire m01_axi_arready; wire [3:0] m01_axi_rid; - wire [31:0]m01_axi_rdata; + wire [63:0]m01_axi_rdata; wire [1:0]m01_axi_rresp; wire m01_axi_rlast; wire m01_axi_rvalid; @@ -409,13 +408,13 @@ module fpgaTop // New SDC Command IOBUF connections wire sd_cmd_i; - reg sd_cmd_reg_o; - reg sd_cmd_reg_t; + wire sd_cmd_reg_o; + wire sd_cmd_reg_t; // New SDC Data IOBUF connections wire [3:0] sd_dat_i; - reg [3:0] sd_dat_reg_o; - reg sd_dat_reg_t; + wire [3:0] sd_dat_reg_o; + wire sd_dat_reg_t; assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -444,7 +443,7 @@ module fpgaTop */ // IOBUFS for new SDC peripheral - IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCcmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); genvar i; generate for (i = 0; i < 4; i = i + 1) begin @@ -502,13 +501,13 @@ module fpgaTop .GPIOPinsEn(GPIOPinsEn), // UART .UARTSin(UARTSin), - .UARTSout(UARTSout), + .UARTSout(UARTSout) // SD Card - .SDCDatIn(SDCDatIn), + /*.SDCDatIn(SDCDatIn), .SDCCmdIn(SDCCmdIn), .SDCCmdOut(SDCCmdOut), .SDCCmdOE(SDCCmdOE), - .SDCCLK(SDCCLK)); + .SDCCLK(SDCCLK));*/ // ahb lite to axi bridge xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 @@ -568,7 +567,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({8'b0, m_axi_awid}), + .s_axi_awid({4'b0, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -588,7 +587,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({8'b0, m_axi_arid}), + .s_axi_arid({4'b0, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -624,7 +623,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({8'b0, s00_axi_bid}), + .m_axi_bid({4'b0, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -640,7 +639,7 @@ module fpgaTop .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({8'b0, s00_axi_rid}), + .m_axi_rid({4'b0, s00_axi_rid}), .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), @@ -856,7 +855,10 @@ module fpgaTop .sd_cmd_reg_t(sd_cmd_reg_t), .sd_cmd_reg_o(sd_cmd_reg_o), - .sd_cmd_i(sd_cmd_i) + .sd_cmd_i(sd_cmd_i), + + .sdio_clk(SDCCLK), + .sdio_cd(SDCCD) ); xlnx_axi_dwidth_conv_32to64 axi_conv_up diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 532efe069..845a96c14 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -57,11 +57,11 @@ module uncore ( output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable input logic UARTSin, // UART serial input output logic UARTSout, // UART serial output - output logic SDCCmdOut, // SD Card command output + /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input input logic [3:0] SDCDatIn, // SD Card data input - output logic SDCCLK // SD Card clock + output logic SDCCLK // SD Card clock*/ ); logic [`XLEN-1:0] HREADRam, HREADSDC; @@ -158,10 +158,10 @@ module uncore ( // interrupt to PLIC .SDCIntM ); - end else begin : sdc + /*end else begin : sdc assign SDCCLK = 0; assign SDCCmdOut = 0; - assign SDCCmdOE = 0; + assign SDCCmdOE = 0;*/ end // AHB Read Multiplexer diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index e4c461571..92dded7ad 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -56,11 +56,11 @@ module wallypipelinedsoc ( output logic [31:0] GPIOPinsEn, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output - input logic SDCCmdIn, // SDC Command input + /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable input logic [3:0] SDCDatIn, // SDC data input - output logic SDCCLK // SDC clock + output logic SDCCLK // SDC clock*/ ); // Uncore signals @@ -87,7 +87,7 @@ module wallypipelinedsoc ( .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, - .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); + /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); end endmodule diff --git a/tests/custom/boot/bios.s b/tests/custom/boot/bios.s new file mode 100644 index 000000000..8057a277d --- /dev/null +++ b/tests/custom/boot/bios.s @@ -0,0 +1,101 @@ +PERIOD = 11000000 +#PERIOD = 20 + +.section .init +.global _start +.type _start, @function + + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, 0x87FFFFF8 + + li a0, 0x00000000 + li a1, 0x80000000 + #li a2, 128*1024*1024/512 # copy 128MB + li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) + #li a2, 800 # copy 400KB + jal ra, copyFlash + + fence.i + # now toggle led so we know the copy completed. + + # write to gpio + li t2, 0xFF + la t3, 0x1006000C + li t4, 5 + +loop: + + # delay + li t0, PERIOD/2 +delay1: + addi t0, t0, -1 + bge t0, x0, delay1 + sw t2, 0x0(t3) + + li t0, PERIOD/2 +delay2: + addi t0, t0, -1 + bge t0, x0, delay2 + sw x0, 0x0(t3) + + addi t4, t4, -1 + bgt t4, x0, loop + + + # now that the card is copied and the led toggled we + # jump to the copied contents of the sd card. + +jumpToLinux: + csrrs a0, 0xF14, x0 # copy hard ID to a0 + li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB + la a2, end_of_bios + li t0, 0x80000000 # start of code + + jalr x0, t0, 0 + +end_of_bios: + + + + diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index 9f4eaa6f9..f9fa2c0fe 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -121,25 +121,6 @@ static int alt_mem __attribute__((section(".bss"))); static const char * errno_to_str(void) { switch (errno) { - case FR_OK: return "No error"; - case FR_DISK_ERR: return "Disk I/O error"; - case FR_INT_ERR: return "Assertion failed"; - case FR_NOT_READY: return "Disk not ready"; - case FR_NO_FILE: return "File not found"; - case FR_NO_PATH: return "Path not found"; - case FR_INVALID_NAME: return "Invalid path"; - case FR_DENIED: return "Access denied"; - case FR_EXIST: return "Already exist"; - case FR_INVALID_OBJECT: return "The FS object is invalid"; - case FR_WRITE_PROTECTED: return "The drive is write protected"; - case FR_INVALID_DRIVE: return "The drive number is invalid"; - case FR_NOT_ENABLED: return "The volume has no work area"; - case FR_NO_FILESYSTEM: return "Not a valid FAT volume"; - case FR_MKFS_ABORTED: return "The f_mkfs() aborted"; - case FR_TIMEOUT: return "Timeout"; - case FR_LOCKED: return "Locked"; - case FR_NOT_ENOUGH_CORE: return "Not enough memory"; - case FR_TOO_MANY_OPEN_FILES: return "Too many open files"; case ERR_EOF: return "Unexpected EOF"; case ERR_NOT_ELF: return "Not an ELF file"; case ERR_ELF_BITS: return "Wrong ELF word size";