From 2cf1d43ec57acc21ec7398a2e61153b385a7f8b5 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Feb 2024 19:39:26 -0600 Subject: [PATCH] add aes instructions --- src/ieu/aes_instructions/aes32dsi.sv | 55 ++++++++++++ src/ieu/aes_instructions/aes32dsmi.sv | 58 +++++++++++++ src/ieu/aes_instructions/aes32esi.sv | 56 ++++++++++++ src/ieu/aes_instructions/aes32esmi.sv | 59 +++++++++++++ src/ieu/aes_instructions/aes64ds.sv | 45 ++++++++++ src/ieu/aes_instructions/aes64dsm.sv | 53 ++++++++++++ src/ieu/aes_instructions/aes64es.sv | 41 +++++++++ src/ieu/aes_instructions/aes64esm.sv | 47 ++++++++++ src/ieu/aes_instructions/aes64im.sv | 34 ++++++++ src/ieu/aes_instructions/aes64ks1i.sv | 120 ++++++++++++++++++++++++++ src/ieu/aes_instructions/aes64ks2.sv | 40 +++++++++ 11 files changed, 608 insertions(+) create mode 100644 src/ieu/aes_instructions/aes32dsi.sv create mode 100644 src/ieu/aes_instructions/aes32dsmi.sv create mode 100644 src/ieu/aes_instructions/aes32esi.sv create mode 100644 src/ieu/aes_instructions/aes32esmi.sv create mode 100644 src/ieu/aes_instructions/aes64ds.sv create mode 100644 src/ieu/aes_instructions/aes64dsm.sv create mode 100644 src/ieu/aes_instructions/aes64es.sv create mode 100644 src/ieu/aes_instructions/aes64esm.sv create mode 100644 src/ieu/aes_instructions/aes64im.sv create mode 100644 src/ieu/aes_instructions/aes64ks1i.sv create mode 100644 src/ieu/aes_instructions/aes64ks2.sv diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv new file mode 100644 index 000000000..914ec8994 --- /dev/null +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -0,0 +1,55 @@ +/////////////////////////////////////////// +// aes32dsi.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32dsi instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32dsi(input logic [1:0] bs, + input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare Intermediary logic + logic [4:0] shamt; + logic [31:0] sbox_in_32; + logic [7:0] sbox_in; + logic [7:0] sbox_out; + logic [31:0] so; + logic [31:0] so_rotate; + + // shamt = bs * 8 + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt and take the lower byte + assign sbox_in_32 = (rs2 >> shamt); + assign sbox_in = sbox_in_32[7:0]; + // Apply inverse sbox to si + aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + // Pad output of inverse substitution box + assign so = {24'h000000,sbox_out}; + // Rotate the substitution box output left by shamt (bs * 8) + rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" + assign data_out = rs1 ^ so_rotate; + +endmodule diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv new file mode 100644 index 000000000..e3b750b79 --- /dev/null +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// aes32dsmi.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32dsmi instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32dsmi(input logic [1:0] bs, + input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare Intermediary logic + logic [4:0] shamt; + logic [31:0] sbox_in_32; + logic [7:0] sbox_in; + logic [7:0] sbox_out; + logic [31:0] so; + logic [31:0] mixed; + logic [31:0] mixed_rotate; + + // shamt = bs * 8 + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt and take the lower byte + assign sbox_in_32 = (rs2 >> shamt); + assign sbox_in = sbox_in_32[7:0]; + // Apply inverse sbox to si + aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + // Pad output of inverse substitution box + assign so = {24'h000000,sbox_out}; + // Run so through the mixword AES function + inv_mixword mix(.word(so),.mixed_word(mixed)); + // Rotate the substitution box output left by shamt (bs * 8) + rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" + assign data_out = rs1 ^ mixed_rotate; + +endmodule diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv new file mode 100644 index 000000000..2281c6f4e --- /dev/null +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -0,0 +1,56 @@ +/////////////////////////////////////////// +// aes32esi.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32esi instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32esi(input logic [1:0] bs, + input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare Intermediary logic + logic [4:0] shamt; + logic [31:0] sbox_in_32; + logic [7:0] sbox_in; + logic [7:0] sbox_out; + logic [31:0] so; + logic [31:0] so_rotate; + + // Shift bs by 3 to get shamt + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt to get sbox input + assign sbox_in_32 = (rs2 >> shamt); + // Take the bottom byte as an input to the substitution box + assign sbox_in = sbox_in_32[7:0]; + // Substitute + aes_sbox subbox(.in(sbox_in),.out(sbox_out)); + // Pad sbox output + assign so = {24'h000000,sbox_out}; + // Rotate so left by shamt + rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); + assign data_out = rs1 ^ so_rotate; + +endmodule diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv new file mode 100644 index 000000000..382c1da5d --- /dev/null +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -0,0 +1,59 @@ +/////////////////////////////////////////// +// aes32esmi.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32esmi instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32esmi(input logic [1:0] bs, + input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare Intermediary logic + logic [4:0] shamt; + logic [31:0] sbox_in_32; + logic [7:0] sbox_in; + logic [7:0] sbox_out; + logic [31:0] so; + logic [31:0] mixed; + logic [31:0] mixed_rotate; + + // Shift bs by 3 to get shamt + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt to get sbox input + assign sbox_in_32 = (rs2 >> shamt); + // Take the bottom byte as an input to the substitution box + assign sbox_in = sbox_in_32[7:0]; + // Substitute + aes_sbox sbox(.in(sbox_in),.out(sbox_out)); + // Pad sbox output + assign so = {24'h000000,sbox_out}; + // Mix Word using aes_mixword component + mixword mwd(.word(so),.mixed_word(mixed)); + // Rotate so left by shamt + rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); + assign data_out = rs1 ^ mixed_rotate; + +endmodule diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv new file mode 100644 index 000000000..4ba657ea7 --- /dev/null +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// aes64ds.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ds instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64ds(input logic [63:0] rs1, + input logic [63:0] rs2, + output logic [63:0] data_out); + + // Intermediary Logic + logic [127:0] shiftRow_out; + logic [31:0] sbox_out_0; + logic [31:0] sbox_out_1; + + // Apply inverse shiftrows to rs2 and rs1 + aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply full word inverse substitution to lower 2 words of shiftrow out + aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0)); + aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + // Concatenate the two substitution outputs to get result + assign data_out = {sbox_out_1, sbox_out_0}; + +endmodule diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv new file mode 100644 index 000000000..4ed5eef13 --- /dev/null +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// aes64dsm.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64dsm instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64dsm(input logic [63:0] rs1, + input logic [63:0] rs2, + output logic [63:0] data_out); + + // Intermediary Logic + logic [127:0] shiftRow_out; + logic [31:0] sbox_out_0; + logic [31:0] sbox_out_1; + logic [31:0] mixcol_out_0; + logic [31:0] mixcol_out_1; + + // Apply inverse shiftrows to rs2 and rs1 + aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply full word inverse substitution to lower 2 words of shiftrow out + aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0)); + aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + // Apply inverse mixword to sbox outputs + inv_mixword inv_mw_0(.word(sbox_out_0),.mixed_word(mixcol_out_0)); + inv_mixword inv_mw_1(.word(sbox_out_1),.mixed_word(mixcol_out_1)); + // Concatenate mixed words for output + assign data_out = {mixcol_out_1,mixcol_out_0}; + +endmodule + + + diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv new file mode 100644 index 000000000..4f665f030 --- /dev/null +++ b/src/ieu/aes_instructions/aes64es.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// aes64es.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64es instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64es(input logic [63:0] rs1, + input logic [63:0] rs2, + output logic [63:0] data_out); + + // Intermediary Signals + logic [127:0] shiftRow_out; + + // AES shiftrow unit + aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply substitution box to 2 lower words + aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(data_out[31:0])); + aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(data_out[63:32])); + +endmodule diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv new file mode 100644 index 000000000..51c5474ac --- /dev/null +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -0,0 +1,47 @@ +/////////////////////////////////////////// +// aes64esm.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64esm instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64esm(input logic [63:0] rs1, + input logic [63:0] rs2, + output logic [63:0] data_out); + + // Intermediary Signals + logic [127:0] shiftRow_out; + logic [63:0] sbox_out; + + // AES shiftrow unit + aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply substitution box to 2 lower words + aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out[31:0])); + aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out[63:32])); + // Apply mix columns operations + mixword mw0(.word(sbox_out[31:0]),.mixed_word(data_out[31:0])); + mixword mw1(.word(sbox_out[63:32]),.mixed_word(data_out[63:32])); + +endmodule + + diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv new file mode 100644 index 000000000..9a898ef89 --- /dev/null +++ b/src/ieu/aes_instructions/aes64im.sv @@ -0,0 +1,34 @@ +/////////////////////////////////////////// +// aes64im.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64im instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64im(input logic [63:0] rs1, + output logic [63:0] data_out); + + inv_mixword inv_mw_0(.word(rs1[31:0]),.mixed_word(data_out[31:0])); + inv_mixword inv_mw_1(.word(rs1[63:32]),.mixed_word(data_out[63:32])); + +endmodule diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv new file mode 100644 index 000000000..6ebfe35eb --- /dev/null +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -0,0 +1,120 @@ +/////////////////////////////////////////// +// aes64ks1i.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ks1i instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64ks1i(input logic [3:0] roundnum, + input logic [63:0] rs1, + output logic [63:0] rd); + + // Instantiate intermediary logic signals + logic [7:0] rcon_preshift; + logic [31:0] rcon; + logic lastRoundFlag; + logic [31:0] rs1_rotate; + logic [31:0] tmp2; + logic [31:0] sbox_out; + + // Get rcon value from table + rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift)); + // Shift RCON value + assign rcon = {24'b0, rcon_preshift}; + // Flag will be set if roundnum = 0xA = 0b1010 + assign lastRoundFlag = roundnum[3] & ~roundnum[2] & roundnum[1] & ~roundnum[0]; + // Get rotated value fo ruse in tmp2 + rrot8 rr(.x(rs1[63:32]), .result(rs1_rotate)); + // Assign tmp2 to a mux based on lastRoundFlag + assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate; + // Substitute bytes of value obtained for tmp2 using Rijndael sbox + aes_sbox_word sbox(.in(tmp2),.out(sbox_out)); + assign rd[31:0] = sbox_out ^ rcon; + assign rd[63:32] = sbox_out ^ rcon; + + // There may be some errors with this instruction. + // Regression tests are passed successfully, but + // the algorithm seems wrong. Check later. + +endmodule + +module rcon_lut_128(input logic [3:0] RD, + output logic [7:0] rcon_out); + + always_comb + begin + case(RD) + 4'h0 : rcon_out = 8'h01; + 4'h1 : rcon_out = 8'h02; + 4'h2 : rcon_out = 8'h04; + 4'h3 : rcon_out = 8'h08; + 4'h4 : rcon_out = 8'h10; + 4'h5 : rcon_out = 8'h20; + 4'h6 : rcon_out = 8'h40; + 4'h7 : rcon_out = 8'h80; + 4'h8 : rcon_out = 8'h1b; + 4'h9 : rcon_out = 8'h36; + 4'hA : rcon_out = 8'h00; + default : rcon_out = 8'h00; + endcase + end + +endmodule + +module rrot8(input logic[31:0] x, + output logic [31:0] result); + + assign result[0] = x[8]; + assign result[1] = x[9]; + assign result[2] = x[10]; + assign result[3] = x[11]; + assign result[4] = x[12]; + assign result[5] = x[13]; + assign result[6] = x[14]; + assign result[7] = x[15]; + assign result[8] = x[16]; + assign result[9] = x[17]; + assign result[10] = x[18]; + assign result[11] = x[19]; + assign result[12] = x[20]; + assign result[13] = x[21]; + assign result[14] = x[22]; + assign result[15] = x[23]; + assign result[16] = x[24]; + assign result[17] = x[25]; + assign result[18] = x[26]; + assign result[19] = x[27]; + assign result[20] = x[28]; + assign result[21] = x[29]; + assign result[22] = x[30]; + assign result[23] = x[31]; + assign result[24] = x[0]; + assign result[25] = x[1]; + assign result[26] = x[2]; + assign result[27] = x[3]; + assign result[28] = x[4]; + assign result[29] = x[5]; + assign result[30] = x[6]; + assign result[31] = x[7]; + +endmodule diff --git a/src/ieu/aes_instructions/aes64ks2.sv b/src/ieu/aes_instructions/aes64ks2.sv new file mode 100644 index 000000000..c2381bcd5 --- /dev/null +++ b/src/ieu/aes_instructions/aes64ks2.sv @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// aes64ks2.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ks2 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64ks2(input logic [63:0] rs2, + input logic [63:0] rs1, + output logic [63:0] rd); + + // Instantiate Intermediary logic + logic [31:0] w0; + logic [31:0] w1; + + assign w0 = rs1[63:32] ^ rs2[31:0]; + assign w1 = rs1[63:32] ^ rs2[31:0] ^ rs2[63:32]; + assign rd = {w1, w0}; + +endmodule