From 517cae796cc27f4fdc3dab309686fb8d2d93f7dd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 5 Dec 2021 15:14:18 -0600 Subject: [PATCH 01/16] Fixed more constraint issues in fpga. Added back in the ILA. Design does not work yet. Stil having issues with order of automatic clock and I/O constraint ordering. Added back in the preload for the boottim. --- fpga/constraints/constraints.xdc | 2 +- fpga/constraints/debug.xdc | 175 ++++++++++++++--------------- fpga/generator/wally.tcl | 2 + wally-pipelined/src/uncore/dtim.sv | 2 - 4 files changed, 86 insertions(+), 95 deletions(-) diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc index 9059dc7f1..716136eca 100644 --- a/fpga/constraints/constraints.xdc +++ b/fpga/constraints/constraints.xdc @@ -282,7 +282,7 @@ set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}] -set_max_delay -datapath_only -from [get_pins wrapper_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins wrapper_i/proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 +set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] diff --git a/fpga/constraints/debug.xdc b/fpga/constraints/debug.xdc index cd1b265d8..9227ba6f6 100644 --- a/fpga/constraints/debug.xdc +++ b/fpga/constraints/debug.xdc @@ -1,26 +1,17 @@ ##### debugger ##### +connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]] +connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOE]] +connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOut]] - - - - - -connect_debug_port u_ila_0/probe34 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]] -connect_debug_port u_ila_0/probe69 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOE]] -connect_debug_port u_ila_0/probe70 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOut]] - - - - -connect_debug_port u_ila_0/probe17 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[64]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[65]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[66]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[67]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[68]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[69]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[70]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[71]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[72]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[73]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[74]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[75]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[76]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[77]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[78]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[79]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[80]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[81]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[82]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[83]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[84]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[85]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[86]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[87]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[88]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[89]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[90]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[91]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[92]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[93]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[94]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[95]}]] -connect_debug_port u_ila_0/probe37 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[3]}]] -connect_debug_port u_ila_0/probe46 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[3]}]] -connect_debug_port u_ila_0/probe75 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_RESTARTING]] -connect_debug_port u_ila_0/probe82 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_bad_card]] -connect_debug_port u_ila_0/probe83 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_BUSY_EN]] -connect_debug_port u_ila_0/probe89 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_resend_last_command]] -connect_debug_port u_ila_0/probe90 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_SD_CMD_RX]] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[64]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[65]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[66]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[67]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[68]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[69]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[70]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[71]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[72]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[73]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[74]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[75]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[76]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[77]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[78]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[79]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[80]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[81]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[82]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[83]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[84]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[85]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[86]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[87]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[88]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[89]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[90]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[91]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[92]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[93]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[94]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[95]}]] +connect_debug_port u_ila_0/probe37 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[3]}]] +connect_debug_port u_ila_0/probe46 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[3]}]] +connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_RESTARTING]] +connect_debug_port u_ila_0/probe82 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_bad_card]] +connect_debug_port u_ila_0/probe83 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_BUSY_EN]] +connect_debug_port u_ila_0/probe89 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_resend_last_command]] +connect_debug_port u_ila_0/probe90 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_SD_CMD_RX]] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] @@ -35,291 +26,291 @@ set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list wrapper_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 12 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]}]] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 4 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 4 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 4 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 6 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 64 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] set_property port_width 64 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} 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{wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]}]] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 64 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 6 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]}]] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] set_property port_width 64 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]}]] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] set_property port_width 6 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]}]] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] set_property port_width 64 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]}]] +connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 6 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]}]] +connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] set_property port_width 64 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]}]] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] set_property port_width 3 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]}]] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 63 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]}]] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property port_width 3 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]}]] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property port_width 64 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/ReadDataM[63]}]] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/ReadDataM[0]} {wallypipelinedsoc/hart/ReadDataM[1]} {wallypipelinedsoc/hart/ReadDataM[2]} {wallypipelinedsoc/hart/ReadDataM[3]} {wallypipelinedsoc/hart/ReadDataM[4]} {wallypipelinedsoc/hart/ReadDataM[5]} {wallypipelinedsoc/hart/ReadDataM[6]} {wallypipelinedsoc/hart/ReadDataM[7]} {wallypipelinedsoc/hart/ReadDataM[8]} {wallypipelinedsoc/hart/ReadDataM[9]} {wallypipelinedsoc/hart/ReadDataM[10]} {wallypipelinedsoc/hart/ReadDataM[11]} {wallypipelinedsoc/hart/ReadDataM[12]} {wallypipelinedsoc/hart/ReadDataM[13]} {wallypipelinedsoc/hart/ReadDataM[14]} {wallypipelinedsoc/hart/ReadDataM[15]} {wallypipelinedsoc/hart/ReadDataM[16]} {wallypipelinedsoc/hart/ReadDataM[17]} {wallypipelinedsoc/hart/ReadDataM[18]} {wallypipelinedsoc/hart/ReadDataM[19]} {wallypipelinedsoc/hart/ReadDataM[20]} {wallypipelinedsoc/hart/ReadDataM[21]} {wallypipelinedsoc/hart/ReadDataM[22]} {wallypipelinedsoc/hart/ReadDataM[23]} {wallypipelinedsoc/hart/ReadDataM[24]} {wallypipelinedsoc/hart/ReadDataM[25]} {wallypipelinedsoc/hart/ReadDataM[26]} {wallypipelinedsoc/hart/ReadDataM[27]} {wallypipelinedsoc/hart/ReadDataM[28]} {wallypipelinedsoc/hart/ReadDataM[29]} {wallypipelinedsoc/hart/ReadDataM[30]} {wallypipelinedsoc/hart/ReadDataM[31]} {wallypipelinedsoc/hart/ReadDataM[32]} {wallypipelinedsoc/hart/ReadDataM[33]} {wallypipelinedsoc/hart/ReadDataM[34]} {wallypipelinedsoc/hart/ReadDataM[35]} {wallypipelinedsoc/hart/ReadDataM[36]} {wallypipelinedsoc/hart/ReadDataM[37]} {wallypipelinedsoc/hart/ReadDataM[38]} {wallypipelinedsoc/hart/ReadDataM[39]} {wallypipelinedsoc/hart/ReadDataM[40]} {wallypipelinedsoc/hart/ReadDataM[41]} {wallypipelinedsoc/hart/ReadDataM[42]} {wallypipelinedsoc/hart/ReadDataM[43]} {wallypipelinedsoc/hart/ReadDataM[44]} {wallypipelinedsoc/hart/ReadDataM[45]} {wallypipelinedsoc/hart/ReadDataM[46]} {wallypipelinedsoc/hart/ReadDataM[47]} {wallypipelinedsoc/hart/ReadDataM[48]} {wallypipelinedsoc/hart/ReadDataM[49]} {wallypipelinedsoc/hart/ReadDataM[50]} {wallypipelinedsoc/hart/ReadDataM[51]} {wallypipelinedsoc/hart/ReadDataM[52]} {wallypipelinedsoc/hart/ReadDataM[53]} {wallypipelinedsoc/hart/ReadDataM[54]} {wallypipelinedsoc/hart/ReadDataM[55]} {wallypipelinedsoc/hart/ReadDataM[56]} {wallypipelinedsoc/hart/ReadDataM[57]} {wallypipelinedsoc/hart/ReadDataM[58]} {wallypipelinedsoc/hart/ReadDataM[59]} {wallypipelinedsoc/hart/ReadDataM[60]} {wallypipelinedsoc/hart/ReadDataM[61]} {wallypipelinedsoc/hart/ReadDataM[62]} {wallypipelinedsoc/hart/ReadDataM[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 64 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/WriteDataM[63]}]] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/hart/WriteDataM[0]} {wallypipelinedsoc/hart/WriteDataM[1]} {wallypipelinedsoc/hart/WriteDataM[2]} {wallypipelinedsoc/hart/WriteDataM[3]} {wallypipelinedsoc/hart/WriteDataM[4]} {wallypipelinedsoc/hart/WriteDataM[5]} {wallypipelinedsoc/hart/WriteDataM[6]} {wallypipelinedsoc/hart/WriteDataM[7]} {wallypipelinedsoc/hart/WriteDataM[8]} {wallypipelinedsoc/hart/WriteDataM[9]} {wallypipelinedsoc/hart/WriteDataM[10]} {wallypipelinedsoc/hart/WriteDataM[11]} {wallypipelinedsoc/hart/WriteDataM[12]} {wallypipelinedsoc/hart/WriteDataM[13]} {wallypipelinedsoc/hart/WriteDataM[14]} {wallypipelinedsoc/hart/WriteDataM[15]} {wallypipelinedsoc/hart/WriteDataM[16]} {wallypipelinedsoc/hart/WriteDataM[17]} {wallypipelinedsoc/hart/WriteDataM[18]} {wallypipelinedsoc/hart/WriteDataM[19]} {wallypipelinedsoc/hart/WriteDataM[20]} {wallypipelinedsoc/hart/WriteDataM[21]} {wallypipelinedsoc/hart/WriteDataM[22]} {wallypipelinedsoc/hart/WriteDataM[23]} {wallypipelinedsoc/hart/WriteDataM[24]} {wallypipelinedsoc/hart/WriteDataM[25]} {wallypipelinedsoc/hart/WriteDataM[26]} {wallypipelinedsoc/hart/WriteDataM[27]} {wallypipelinedsoc/hart/WriteDataM[28]} {wallypipelinedsoc/hart/WriteDataM[29]} {wallypipelinedsoc/hart/WriteDataM[30]} {wallypipelinedsoc/hart/WriteDataM[31]} {wallypipelinedsoc/hart/WriteDataM[32]} {wallypipelinedsoc/hart/WriteDataM[33]} {wallypipelinedsoc/hart/WriteDataM[34]} {wallypipelinedsoc/hart/WriteDataM[35]} {wallypipelinedsoc/hart/WriteDataM[36]} {wallypipelinedsoc/hart/WriteDataM[37]} {wallypipelinedsoc/hart/WriteDataM[38]} {wallypipelinedsoc/hart/WriteDataM[39]} {wallypipelinedsoc/hart/WriteDataM[40]} {wallypipelinedsoc/hart/WriteDataM[41]} {wallypipelinedsoc/hart/WriteDataM[42]} {wallypipelinedsoc/hart/WriteDataM[43]} {wallypipelinedsoc/hart/WriteDataM[44]} {wallypipelinedsoc/hart/WriteDataM[45]} {wallypipelinedsoc/hart/WriteDataM[46]} {wallypipelinedsoc/hart/WriteDataM[47]} {wallypipelinedsoc/hart/WriteDataM[48]} {wallypipelinedsoc/hart/WriteDataM[49]} {wallypipelinedsoc/hart/WriteDataM[50]} {wallypipelinedsoc/hart/WriteDataM[51]} {wallypipelinedsoc/hart/WriteDataM[52]} {wallypipelinedsoc/hart/WriteDataM[53]} {wallypipelinedsoc/hart/WriteDataM[54]} {wallypipelinedsoc/hart/WriteDataM[55]} {wallypipelinedsoc/hart/WriteDataM[56]} {wallypipelinedsoc/hart/WriteDataM[57]} {wallypipelinedsoc/hart/WriteDataM[58]} {wallypipelinedsoc/hart/WriteDataM[59]} {wallypipelinedsoc/hart/WriteDataM[60]} {wallypipelinedsoc/hart/WriteDataM[61]} {wallypipelinedsoc/hart/WriteDataM[62]} {wallypipelinedsoc/hart/WriteDataM[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] set_property port_width 3 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]}]] +connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] set_property port_width 5 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]}]] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] set_property port_width 4 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[3]}]] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] set_property port_width 4 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]}]] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] set_property port_width 64 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]}]] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] set_property port_width 64 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]}]] +connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] set_property port_width 32 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]}]] +connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] set_property port_width 2 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]}]] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] set_property port_width 32 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]}]] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] set_property port_width 64 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/PCM[63]}]] +connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/hart/PCM[0]} {wallypipelinedsoc/hart/PCM[1]} {wallypipelinedsoc/hart/PCM[2]} {wallypipelinedsoc/hart/PCM[3]} {wallypipelinedsoc/hart/PCM[4]} {wallypipelinedsoc/hart/PCM[5]} {wallypipelinedsoc/hart/PCM[6]} {wallypipelinedsoc/hart/PCM[7]} {wallypipelinedsoc/hart/PCM[8]} {wallypipelinedsoc/hart/PCM[9]} {wallypipelinedsoc/hart/PCM[10]} {wallypipelinedsoc/hart/PCM[11]} {wallypipelinedsoc/hart/PCM[12]} {wallypipelinedsoc/hart/PCM[13]} {wallypipelinedsoc/hart/PCM[14]} {wallypipelinedsoc/hart/PCM[15]} {wallypipelinedsoc/hart/PCM[16]} {wallypipelinedsoc/hart/PCM[17]} {wallypipelinedsoc/hart/PCM[18]} {wallypipelinedsoc/hart/PCM[19]} {wallypipelinedsoc/hart/PCM[20]} {wallypipelinedsoc/hart/PCM[21]} {wallypipelinedsoc/hart/PCM[22]} {wallypipelinedsoc/hart/PCM[23]} {wallypipelinedsoc/hart/PCM[24]} {wallypipelinedsoc/hart/PCM[25]} {wallypipelinedsoc/hart/PCM[26]} {wallypipelinedsoc/hart/PCM[27]} {wallypipelinedsoc/hart/PCM[28]} {wallypipelinedsoc/hart/PCM[29]} {wallypipelinedsoc/hart/PCM[30]} {wallypipelinedsoc/hart/PCM[31]} {wallypipelinedsoc/hart/PCM[32]} {wallypipelinedsoc/hart/PCM[33]} {wallypipelinedsoc/hart/PCM[34]} {wallypipelinedsoc/hart/PCM[35]} {wallypipelinedsoc/hart/PCM[36]} {wallypipelinedsoc/hart/PCM[37]} {wallypipelinedsoc/hart/PCM[38]} {wallypipelinedsoc/hart/PCM[39]} {wallypipelinedsoc/hart/PCM[40]} {wallypipelinedsoc/hart/PCM[41]} {wallypipelinedsoc/hart/PCM[42]} {wallypipelinedsoc/hart/PCM[43]} {wallypipelinedsoc/hart/PCM[44]} {wallypipelinedsoc/hart/PCM[45]} {wallypipelinedsoc/hart/PCM[46]} {wallypipelinedsoc/hart/PCM[47]} {wallypipelinedsoc/hart/PCM[48]} {wallypipelinedsoc/hart/PCM[49]} {wallypipelinedsoc/hart/PCM[50]} {wallypipelinedsoc/hart/PCM[51]} {wallypipelinedsoc/hart/PCM[52]} {wallypipelinedsoc/hart/PCM[53]} {wallypipelinedsoc/hart/PCM[54]} {wallypipelinedsoc/hart/PCM[55]} {wallypipelinedsoc/hart/PCM[56]} {wallypipelinedsoc/hart/PCM[57]} {wallypipelinedsoc/hart/PCM[58]} {wallypipelinedsoc/hart/PCM[59]} {wallypipelinedsoc/hart/PCM[60]} {wallypipelinedsoc/hart/PCM[61]} {wallypipelinedsoc/hart/PCM[62]} {wallypipelinedsoc/hart/PCM[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] set_property port_width 64 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[31]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[32]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[33]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[34]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[35]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[36]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[37]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[38]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[39]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[40]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[41]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[42]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[43]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[44]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[45]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[46]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[47]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[48]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[49]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[50]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[51]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[52]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[53]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[54]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[55]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[56]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[57]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[58]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[59]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[60]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[61]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[62]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemAdrM[63]}]] +connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] set_property port_width 2 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemRWM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/MemRWM[1]}]] +connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/hart/MemRWM[0]} {wallypipelinedsoc/hart/MemRWM[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] set_property port_width 32 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[0]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[1]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[2]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[3]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[4]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[5]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[6]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[7]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[8]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[9]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[10]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[11]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[12]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[13]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[14]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[15]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[16]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[17]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[18]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[19]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[20]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[21]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[22]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[23]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[24]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[25]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[26]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[27]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[28]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[29]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[30]} {wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrM[31]}]] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/InstrM[0]} {wallypipelinedsoc/hart/InstrM[1]} {wallypipelinedsoc/hart/InstrM[2]} {wallypipelinedsoc/hart/InstrM[3]} {wallypipelinedsoc/hart/InstrM[4]} {wallypipelinedsoc/hart/InstrM[5]} {wallypipelinedsoc/hart/InstrM[6]} {wallypipelinedsoc/hart/InstrM[7]} {wallypipelinedsoc/hart/InstrM[8]} {wallypipelinedsoc/hart/InstrM[9]} {wallypipelinedsoc/hart/InstrM[10]} {wallypipelinedsoc/hart/InstrM[11]} {wallypipelinedsoc/hart/InstrM[12]} {wallypipelinedsoc/hart/InstrM[13]} {wallypipelinedsoc/hart/InstrM[14]} {wallypipelinedsoc/hart/InstrM[15]} {wallypipelinedsoc/hart/InstrM[16]} {wallypipelinedsoc/hart/InstrM[17]} {wallypipelinedsoc/hart/InstrM[18]} {wallypipelinedsoc/hart/InstrM[19]} {wallypipelinedsoc/hart/InstrM[20]} {wallypipelinedsoc/hart/InstrM[21]} {wallypipelinedsoc/hart/InstrM[22]} {wallypipelinedsoc/hart/InstrM[23]} {wallypipelinedsoc/hart/InstrM[24]} {wallypipelinedsoc/hart/InstrM[25]} {wallypipelinedsoc/hart/InstrM[26]} {wallypipelinedsoc/hart/InstrM[27]} {wallypipelinedsoc/hart/InstrM[28]} {wallypipelinedsoc/hart/InstrM[29]} {wallypipelinedsoc/hart/InstrM[30]} {wallypipelinedsoc/hart/InstrM[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBAck]] +connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBAck]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBRead]] +connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBRead]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/lsu/dcache/AHBWrite]] +connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBWrite]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/BreakpointFaultM]] +connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/hart/priv/trap/BreakpointFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/EcallFaultM]] +connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/hart/priv/trap/EcallFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q]] +connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD]] +connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16]] +connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT]] +connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] set_property port_width 1 [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM]] +connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] set_property port_width 1 [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM]] +connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] set_property port_width 1 [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/InstrPageFaultM]] +connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrPageFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] set_property port_width 1 [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/InstrValidM]] +connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/hart/InstrValidM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] set_property port_width 1 [get_debug_ports u_ila_0/probe45] -connect_debug_port u_ila_0/probe45 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM]] +connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] set_property port_width 1 [get_debug_ports u_ila_0/probe46] -connect_debug_port u_ila_0/probe46 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM]] +connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] set_property port_width 1 [get_debug_ports u_ila_0/probe47] -connect_debug_port u_ila_0/probe47 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/LoadPageFaultM]] +connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadPageFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48] set_property port_width 1 [get_debug_ports u_ila_0/probe48] -connect_debug_port u_ila_0/probe48 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/mretM]] +connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/hart/priv/trap/mretM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49] set_property port_width 1 [get_debug_ports u_ila_0/probe49] -connect_debug_port u_ila_0/probe49 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN]] +connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] set_property port_width 1 [get_debug_ports u_ila_0/probe50] -connect_debug_port u_ila_0/probe50 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CLK]] +connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CLK]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] set_property port_width 1 [get_debug_ports u_ila_0/probe51] -connect_debug_port u_ila_0/probe51 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD]] +connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] set_property port_width 1 [get_debug_ports u_ila_0/probe52] -connect_debug_port u_ila_0/probe52 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD_OE]] +connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD_OE]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] set_property port_width 1 [get_debug_ports u_ila_0/probe53] -connect_debug_port u_ila_0/probe53 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE]] +connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] set_property port_width 1 [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q]] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] set_property port_width 1 [get_debug_ports u_ila_0/probe55] -connect_debug_port u_ila_0/probe55 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/sretM]] +connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/hart/priv/trap/sretM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] set_property port_width 1 [get_debug_ports u_ila_0/probe56] -connect_debug_port u_ila_0/probe56 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM]] +connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] set_property port_width 1 [get_debug_ports u_ila_0/probe57] -connect_debug_port u_ila_0/probe57 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM]] +connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] set_property port_width 1 [get_debug_ports u_ila_0/probe58] -connect_debug_port u_ila_0/probe58 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/priv/trap/StorePageFaultM]] +connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/hart/priv/trap/StorePageFaultM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] set_property port_width 1 [get_debug_ports u_ila_0/probe59] -connect_debug_port u_ila_0/probe59 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/hart/TrapM]] +connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/hart/TrapM]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60] set_property port_width 1 [get_debug_ports u_ila_0/probe60] -connect_debug_port u_ila_0/probe60 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_EN]] +connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_EN]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] set_property port_width 1 [get_debug_ports u_ila_0/probe61] -connect_debug_port u_ila_0/probe61 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_RST]] +connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_RST]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62] set_property port_width 1 [get_debug_ports u_ila_0/probe62] -connect_debug_port u_ila_0/probe62 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_UP_DOWN]] +connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_UP_DOWN]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63] set_property port_width 1 [get_debug_ports u_ila_0/probe63] -connect_debug_port u_ila_0/probe63 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/DTRb]] +connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/uncore/uart.uart/DTRb]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64] set_property port_width 1 [get_debug_ports u_ila_0/probe64] -connect_debug_port u_ila_0/probe64 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/INTR]] +connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/uncore/uart.uart/INTR]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65] set_property port_width 1 [get_debug_ports u_ila_0/probe65] -connect_debug_port u_ila_0/probe65 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/OUT1b]] +connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT1b]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] set_property port_width 1 [get_debug_ports u_ila_0/probe66] -connect_debug_port u_ila_0/probe66 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/OUT2b]] +connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT2b]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] set_property port_width 1 [get_debug_ports u_ila_0/probe67] -connect_debug_port u_ila_0/probe67 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/RTSb]] +connect_debug_port u_ila_0/probe67 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RTSb]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] set_property port_width 1 [get_debug_ports u_ila_0/probe68] -connect_debug_port u_ila_0/probe68 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/RXRDYb]] +connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RXRDYb]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] set_property port_width 1 [get_debug_ports u_ila_0/probe69] -connect_debug_port u_ila_0/probe69 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/SIN]] +connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SIN]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] set_property port_width 1 [get_debug_ports u_ila_0/probe70] -connect_debug_port u_ila_0/probe70 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/SOUT]] +connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SOUT]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] set_property port_width 1 [get_debug_ports u_ila_0/probe71] -connect_debug_port u_ila_0/probe71 [get_nets [list wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/uart.uart/TXRDYb]] +connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/uncore/uart.uart/TXRDYb]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index affeb45bd..38dc7dce8 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -130,6 +130,8 @@ report_utilization -hierarchical -file re report_cdc -file reports/cdc.rpt report_clock_interaction -file reports/clock_interaction.rpt +source ../constraints/debug2.xdc + # set for RuntimeOptimized implementation #set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index 0ebededc9..3bb2eb0cf 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -51,7 +51,6 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( initial begin //$readmemh(PRELOAD, RAM); -/* -----\/----- EXCLUDED -----\/----- // FPGA only RAM[0] = 64'h94e1819300002197; RAM[1] = 64'h4281420141014081; @@ -95,7 +94,6 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( RAM[39] = 64'h1047278367498082; RAM[40] = 64'h67c98082dfed8b85; RAM[41] = 64'h0000808210a7a023; - -----/\----- EXCLUDED -----/\----- */ end assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00); From 6c9db52801c9f1c36ef42204f4f1c6970008bdd6 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sun, 5 Dec 2021 22:03:51 -0800 Subject: [PATCH 02/16] linux-testvectors symlinks shouldn't be in repo, especially not in this location --- wally-pipelined/linux-testgen/linux-testvectors/all.txt | 1 - wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt | 1 - .../linux-testgen/linux-testvectors/checkpoint8500000 | 1 - wally-pipelined/linux-testgen/linux-testvectors/ram.txt | 1 - wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump | 1 - .../linux-testgen/linux-testvectors/vmlinux.objdump.addr | 1 - .../linux-testgen/linux-testvectors/vmlinux.objdump.lab | 1 - 7 files changed, 7 deletions(-) delete mode 120000 wally-pipelined/linux-testgen/linux-testvectors/all.txt delete mode 120000 wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt delete mode 120000 wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 delete mode 120000 wally-pipelined/linux-testgen/linux-testvectors/ram.txt delete mode 120000 wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump delete mode 120000 wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr delete mode 120000 wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab diff --git a/wally-pipelined/linux-testgen/linux-testvectors/all.txt b/wally-pipelined/linux-testgen/linux-testvectors/all.txt deleted file mode 120000 index 4275ab31a..000000000 --- a/wally-pipelined/linux-testgen/linux-testvectors/all.txt +++ /dev/null @@ -1 +0,0 @@ -/courses/e190ax/buildroot_boot/all.txt \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt b/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt deleted file mode 120000 index 33bff4ce4..000000000 --- a/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt +++ /dev/null @@ -1 +0,0 @@ -/courses/e190ax/buildroot_boot/bootmem.txt \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 b/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 deleted file mode 120000 index e48344418..000000000 --- a/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 +++ /dev/null @@ -1 +0,0 @@ -/courses/e190ax/buildroot_boot/checkpoint8500000 \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/ram.txt b/wally-pipelined/linux-testgen/linux-testvectors/ram.txt deleted file mode 120000 index 209d4eed6..000000000 --- a/wally-pipelined/linux-testgen/linux-testvectors/ram.txt +++ /dev/null @@ -1 +0,0 @@ -/courses/e190ax/buildroot_boot/ram.txt \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump deleted file mode 120000 index 8f52aac07..000000000 --- a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump +++ /dev/null @@ -1 +0,0 @@ -/courses/e190ax/buildroot_boot/vmlinux.objdump \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr deleted file mode 120000 index 62079f3a2..000000000 --- a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr +++ /dev/null @@ -1 +0,0 @@ -/courses/e190ax/buildroot_boot/vmlinux.objdump.addr \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab deleted file mode 120000 index fe8ecc6e4..000000000 --- a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab +++ /dev/null @@ -1 +0,0 @@ -/courses/e190ax/buildroot_boot/vmlinux.objdump.lab \ No newline at end of file From d702599d56286e655dc1aa627560e019a9172334 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 6 Dec 2021 14:13:58 -0800 Subject: [PATCH 03/16] add buildroot-only option to regression --- wally-pipelined/regression/regression-wally.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index c55e8b617..bedbe5db5 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -93,10 +93,13 @@ def main(): # max out at a limited number of concurrent processes to not overwhelm the system if '-all' in sys.argv: - TIMEOUT_DUR = 20*3600 + TIMEOUT_DUR = 20*3600 # seconds configs.append(getBuildrootTC(short=False)) + elif '-buildroot' in sys.argv: + TIMEOUT_DUR = 20*3600 # seconds + configs=[getBuildrootTC(short=False)] else: - TIMEOUT_DUR = 300 + TIMEOUT_DUR = 5*60 # seconds configs.append(getBuildrootTC(short=True)) print(configs) From b714490f926422482ddae0560374935f59523b80 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 6 Dec 2021 15:37:33 -0800 Subject: [PATCH 04/16] add make-tests scripts --- wally-pipelined/regression/make-tests.sh | 12 ++++++++++++ wally-pipelined/regression/regression-wally.py | 16 +++++++++------- 2 files changed, 21 insertions(+), 7 deletions(-) create mode 100755 wally-pipelined/regression/make-tests.sh diff --git a/wally-pipelined/regression/make-tests.sh b/wally-pipelined/regression/make-tests.sh new file mode 100755 index 000000000..e64f94455 --- /dev/null +++ b/wally-pipelined/regression/make-tests.sh @@ -0,0 +1,12 @@ +#!/bin/bash + +rm -r work* +cd ../../tests/imperas-riscv-tests/ +make allclean +make +cd ../wally-riscv-arch-test +make allclean +make +make XLEN=32 +exe2memfile.pl work/*/*/*.elf +cd ../../wally-pipelined/regression diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index bedbe5db5..1494bc46e 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -89,8 +89,13 @@ def run_test_case(config): def main(): """Run the tests and count the failures""" - # Scale the number of concurrent processes to the number of test cases, but - # max out at a limited number of concurrent processes to not overwhelm the system + try: + os.mkdir("logs") + except: + pass + + if '-makeTests' in sys.argv: + os.system('./make-tests.sh | tee ./logs/make-tests.log') if '-all' in sys.argv: TIMEOUT_DUR = 20*3600 # seconds @@ -101,12 +106,9 @@ def main(): else: TIMEOUT_DUR = 5*60 # seconds configs.append(getBuildrootTC(short=True)) - print(configs) - try: - os.mkdir("logs") - except: - pass + # Scale the number of concurrent processes to the number of test cases, but + # max out at a limited number of concurrent processes to not overwhelm the system with Pool(processes=min(len(configs),25)) as pool: num_fail = 0 results = {} From ffe7cf83e5ae710c502647132ba272d20964dd52 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 6 Dec 2021 19:32:38 -0800 Subject: [PATCH 05/16] regression.py bugfix --- wally-pipelined/regression/regression-wally.py | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 1494bc46e..810e7ca9d 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -89,6 +89,7 @@ def run_test_case(config): def main(): """Run the tests and count the failures""" + global configs try: os.mkdir("logs") except: From 3d829dbbd3d15a88c78bf107a6c9f17939d6c803 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 7 Dec 2021 12:15:50 -0600 Subject: [PATCH 06/16] Fixed two issues. First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly. Second the bidir buffer for the sd card was connected backwards. --- fpga/generator/wally.tcl | 109 +++++++++++++++----------- fpga/src/fpgaTop.v | 4 +- wally-pipelined/src/sdc/sd_dat_fsm.sv | 1 - 3 files changed, 65 insertions(+), 49 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 38dc7dce8..b9f55c0e7 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -20,68 +20,86 @@ read_verilog {../src/fpgaTop.v} set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelined/config/shared} [current_fileset] # contrainsts generated by the IP blocks -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc] +#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc] +#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc] +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc] +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc] +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc] +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc +#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc] + +#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc] add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints.xdc] -add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc -set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc] - -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc -set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc] - -add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc] - - -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc] - - -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc +# implementation only +#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc +#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc] + + + + -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc - -add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc -add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0_ooc_debug.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc + #add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.runs/xlnx_ahblite_axi_bridge_synth_1/dont_touch.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.runs/xlnx_proc_sys_reset_synth_1/dont_touch.xdc @@ -98,14 +116,13 @@ add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/ # define top level set_property top fpgaTop [current_fileset] -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc] -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc] -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc] -set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc] +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc] +#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc] update_compile_order -fileset sources_1 -update_compile_order -fileset constrs_1 +# this line is wrong vvv +#update_compile_order -fileset constrs_1 # This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on. report_compile_order -constraints > reports/compile_order.rpt diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index d9751c9ce..d299e5512 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -192,8 +192,8 @@ module fpgaTop // SD Card Tristate IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low - .I(SDCCmdIn), - .O(SDCCmdOut), + .I(SDCCmdOut), + .O(SDCCmdIn), .IO(SDCCmd)); // reset controller XILINX IP diff --git a/wally-pipelined/src/sdc/sd_dat_fsm.sv b/wally-pipelined/src/sdc/sd_dat_fsm.sv index 124d65514..7726f1cb5 100644 --- a/wally-pipelined/src/sdc/sd_dat_fsm.sv +++ b/wally-pipelined/src/sdc/sd_dat_fsm.sv @@ -64,7 +64,6 @@ module sd_dat_fsm (* mark_debug = "true" *) logic [3:0] r_curr_state; logic [3:0] w_next_state; - (* mark_debug = "true" *) logic w_error_crc16_fd_en, w_error_crc16_fd_rst, w_error_crc16_fd_d; // Save ERROR_CRC16 so CMD FSM sees it in IDLE_NRC (not just in IDLE_DAT) logic r_error_crc16_fd_Q; logic [22:0] Identify_Timer_In; From 8bb3d51aad98ca3028f383d3e8aab48e44fd0175 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 7 Dec 2021 13:12:47 -0600 Subject: [PATCH 07/16] Added generate around the dtim preload. Added readme to explain FPGA. --- fpga/README.md | 40 +++++++++++++ wally-pipelined/src/uncore/dtim.sv | 96 ++++++++++++++++-------------- 2 files changed, 90 insertions(+), 46 deletions(-) create mode 100644 fpga/README.md diff --git a/fpga/README.md b/fpga/README.md new file mode 100644 index 000000000..4dded4b1d --- /dev/null +++ b/fpga/README.md @@ -0,0 +1,40 @@ +The FPGA currently only targets the VCU118 board. + +* Build Process + +cd generator +make + +* Description + +The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4, +axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks +and builds wally. fpga/src/fpgaTop.v is the top level which instanciates +wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic +analyzer) which provides the current instruction PCM, instrM, etc along with +a large number of debuging signals. + +* Loading the FPGA + +After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's +gui and open the WallyFPGA.xpr project file. Open the hardware manager under +program and debug. Open target and then program with the bit file. + +* Test Run + +Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide +status of the reset and ddr4 calibration. LED 7 should always be lit. +LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once +wally begins running. + +Next the bootloader program will copy the flash card into the DDR4 memory. +When this done the lower 5 LEDs will blink 5 times and then try to boot +the program loaded in the DDR4 memory at physical address 0x8000_0000. + +* Connecting uart +You'll need to connect both usb cables. The first connects the FPGA programer +while the connect connects UART. UART is configured to use 57600 baud with +no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should +let you view the com port. + + diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index 3bb2eb0cf..59beebb6d 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -49,52 +49,56 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( logic memwrite; logic [3:0] busycount; - initial begin - //$readmemh(PRELOAD, RAM); - // FPGA only - RAM[0] = 64'h94e1819300002197; - RAM[1] = 64'h4281420141014081; - RAM[2] = 64'h4481440143814301; - RAM[3] = 64'h4681460145814501; - RAM[4] = 64'h4881480147814701; - RAM[5] = 64'h4a814a0149814901; - RAM[6] = 64'h4c814c014b814b01; - RAM[7] = 64'h4e814e014d814d01; - RAM[8] = 64'h0110011b4f814f01; - RAM[9] = 64'h059b45011161016e; - RAM[10] = 64'h0004063705fe0010; - RAM[11] = 64'h05a000ef8006061b; - RAM[12] = 64'h0ff003930000100f; - RAM[13] = 64'h4e952e3110012e37; - RAM[14] = 64'hc602829b0053f2b7; - RAM[15] = 64'h2023fe02dfe312fd; - RAM[16] = 64'h829b0053f2b7007e; - RAM[17] = 64'hfe02dfe312fdc602; - RAM[18] = 64'h4de31efd000e2023; - RAM[19] = 64'h059bf1402573fdd0; - RAM[20] = 64'h0000061705e20870; - RAM[21] = 64'h0010029b01260613; - RAM[22] = 64'h11010002806702fe; - RAM[23] = 64'h84b2842ae426e822; - RAM[24] = 64'h892ee04aec064505; - RAM[25] = 64'h06e000ef07e000ef; - RAM[26] = 64'h979334fd02905563; - RAM[27] = 64'h07930177d4930204; - RAM[28] = 64'h4089093394be2004; - RAM[29] = 64'h04138522008905b3; - RAM[30] = 64'h19e3014000ef2004; - RAM[31] = 64'h64a2644260e2fe94; - RAM[32] = 64'h6749808261056902; - RAM[33] = 64'hdfed8b8510472783; - RAM[34] = 64'h2423479110a73823; - RAM[35] = 64'h10472783674910f7; - RAM[36] = 64'h20058693ffed8b89; - RAM[37] = 64'h05a1118737836749; - RAM[38] = 64'hfed59be3fef5bc23; - RAM[39] = 64'h1047278367498082; - RAM[40] = 64'h67c98082dfed8b85; - RAM[41] = 64'h0000808210a7a023; - end + generate + if(`FPGA) begin + initial begin + //$readmemh(PRELOAD, RAM); + // FPGA only + RAM[0] = 64'h94e1819300002197; + RAM[1] = 64'h4281420141014081; + RAM[2] = 64'h4481440143814301; + RAM[3] = 64'h4681460145814501; + RAM[4] = 64'h4881480147814701; + RAM[5] = 64'h4a814a0149814901; + RAM[6] = 64'h4c814c014b814b01; + RAM[7] = 64'h4e814e014d814d01; + RAM[8] = 64'h0110011b4f814f01; + RAM[9] = 64'h059b45011161016e; + RAM[10] = 64'h0004063705fe0010; + RAM[11] = 64'h05a000ef8006061b; + RAM[12] = 64'h0ff003930000100f; + RAM[13] = 64'h4e952e3110012e37; + RAM[14] = 64'hc602829b0053f2b7; + RAM[15] = 64'h2023fe02dfe312fd; + RAM[16] = 64'h829b0053f2b7007e; + RAM[17] = 64'hfe02dfe312fdc602; + RAM[18] = 64'h4de31efd000e2023; + RAM[19] = 64'h059bf1402573fdd0; + RAM[20] = 64'h0000061705e20870; + RAM[21] = 64'h0010029b01260613; + RAM[22] = 64'h11010002806702fe; + RAM[23] = 64'h84b2842ae426e822; + RAM[24] = 64'h892ee04aec064505; + RAM[25] = 64'h06e000ef07e000ef; + RAM[26] = 64'h979334fd02905563; + RAM[27] = 64'h07930177d4930204; + RAM[28] = 64'h4089093394be2004; + RAM[29] = 64'h04138522008905b3; + RAM[30] = 64'h19e3014000ef2004; + RAM[31] = 64'h64a2644260e2fe94; + RAM[32] = 64'h6749808261056902; + RAM[33] = 64'hdfed8b8510472783; + RAM[34] = 64'h2423479110a73823; + RAM[35] = 64'h10472783674910f7; + RAM[36] = 64'h20058693ffed8b89; + RAM[37] = 64'h05a1118737836749; + RAM[38] = 64'hfed59be3fef5bc23; + RAM[39] = 64'h1047278367498082; + RAM[40] = 64'h67c98082dfed8b85; + RAM[41] = 64'h0000808210a7a023; + end // initial begin + end // if (FPGA) + endgenerate assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00); From 8e2a9d5bbb98a86c3033ba1527154e2c071fc4c4 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 7 Dec 2021 11:15:59 -0800 Subject: [PATCH 08/16] add buildroot tv linking to make-tests.sh --- wally-pipelined/regression/make-tests.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/regression/make-tests.sh b/wally-pipelined/regression/make-tests.sh index e64f94455..dfc7d6182 100755 --- a/wally-pipelined/regression/make-tests.sh +++ b/wally-pipelined/regression/make-tests.sh @@ -9,4 +9,6 @@ make allclean make make XLEN=32 exe2memfile.pl work/*/*/*.elf -cd ../../wally-pipelined/regression +cd ../linux-testgen/linux-testvectors +./tvLinker.sh +cd ../../../wally-pipelined/regression From 51e2b9ea6fb0f4c07376f0fe9a4962acd674062d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 7 Dec 2021 13:16:38 -0600 Subject: [PATCH 09/16] Added information on how to copy the linux image to flash card. --- fpga/README.md | 6 ++++++ .../linux-testgen/linux-testvectors/convert2bin.py | 13 +++++++++++++ 2 files changed, 19 insertions(+) create mode 100755 wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py diff --git a/fpga/README.md b/fpga/README.md index 4dded4b1d..eb08171a6 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -14,6 +14,12 @@ wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic analyzer) which provides the current instruction PCM, instrM, etc along with a large number of debuging signals. +* Programming the flash card +You'll need to write the linux image to the flash card. Use the convert2bin.py +script in wally-pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt +file from QEMU's preload to generate the binary. Then to copy + sudo dd if=ram.bin of=. + * Loading the FPGA After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's diff --git a/wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py b/wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py new file mode 100755 index 000000000..78349a5d6 --- /dev/null +++ b/wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py @@ -0,0 +1,13 @@ +#!/usr/bin/python3 + +asciiBinFile = 'ram.txt' +binFile = 'ram.bin' + +asciiBinFP = open(asciiBinFile, 'r') +binFP = open (binFile, 'wb') + +for line in asciiBinFP.readlines(): + binFP.write(int(line, 16).to_bytes(8, byteorder='little', signed=False)) + +asciiBinFP.close() +binFP.close() From 06923720372e41f98ec20246421276576457778d Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 7 Dec 2021 11:16:43 -0800 Subject: [PATCH 10/16] attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly --- wally-pipelined/regression/regression-wally.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 810e7ca9d..f43a7fd70 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -10,9 +10,11 @@ # output. # ################################## -import sys +import sys,os from collections import namedtuple +regressionDir = os.path.dirname(os.path.abspath(__file__)) +os.chdir(regressionDir) TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr']) # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) From 0c48725fa5e18e48976eafd35497445cffc05a6e Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 7 Dec 2021 13:12:06 -0800 Subject: [PATCH 11/16] fix checkpointing so that it can find the synchronized reset signal --- wally-pipelined/testbench/testbench-linux.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 50559b9d0..a757e4f7d 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -48,7 +48,7 @@ module testbench(); /////////////////////////////////////////////////////////////////////////////// ////////////////////////////////// HARDWARE /////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// - logic clk, reset, reset_ext; + logic clk, reset_ext; initial begin reset_ext <= 1; # 22; reset_ext <= 0; end always begin clk <= 1; # 5; clk <= 0; # 5; end @@ -85,6 +85,9 @@ module testbench(); .UARTSin, .UARTSout, .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); + logic reset; + assign reset = dut.reset; + // Write Back stage signals not needed by Wally itself parameter nop = 'h13; logic [`XLEN-1:0] PCW; From ec6c3bd74c334861e367dc27ef9ab48ff05815a7 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 7 Dec 2021 13:13:30 -0800 Subject: [PATCH 12/16] 2nd attempt at making regression-wally.py able to be run from a different dir --- wally-pipelined/regression/regression-wally.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index f43a7fd70..828c2b7cf 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -80,6 +80,7 @@ def run_test_case(config): logname = "logs/wally_"+config.name+".log" cmd = config.cmd.format(logname) print(cmd) + os.chdir(regressionDir) os.system(cmd) if search_log_for_text(config.grepstr, logname): print("%s: Success" % config.name) @@ -93,11 +94,13 @@ def main(): """Run the tests and count the failures""" global configs try: + os.chdir(regressionDir) os.mkdir("logs") except: pass if '-makeTests' in sys.argv: + os.chdir(regressionDir) os.system('./make-tests.sh | tee ./logs/make-tests.log') if '-all' in sys.argv: From 69f025a6428ff4d9b91608fa50915e645095bd2c Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 7 Dec 2021 13:23:19 -0800 Subject: [PATCH 13/16] intentionally breaking commit --- wally-pipelined/src/wally/wallypipelinedsoc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 8f3a2234b..8eac950d1 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -79,7 +79,7 @@ module wallypipelinedsoc ( wallypipelinedhart hart(.clk, .reset, .TimerIntM, .ExtIntM, .SwIntM, .MTIME_CLINT, .MTIMECMP_CLINT, - .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, + .HRDATA('0), .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HWRITED ); From cf6118727397bc03997e646d797e3de32e3dacee Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 7 Dec 2021 13:27:06 -0800 Subject: [PATCH 14/16] undo intentionally breaking commit --- wally-pipelined/src/wally/wallypipelinedsoc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 8eac950d1..8f3a2234b 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -79,7 +79,7 @@ module wallypipelinedsoc ( wallypipelinedhart hart(.clk, .reset, .TimerIntM, .ExtIntM, .SwIntM, .MTIME_CLINT, .MTIMECMP_CLINT, - .HRDATA('0), .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, + .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HWRITED ); From 3379b74bb2f68c0a498609b28b07591369c047e8 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 7 Dec 2021 13:27:34 -0800 Subject: [PATCH 15/16] intentionally breaking commit --- wally-pipelined/src/wally/wallypipelinedsoc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 8f3a2234b..ed420d9d7 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -76,7 +76,7 @@ module wallypipelinedsoc ( synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); // instantiate processor and memories - wallypipelinedhart hart(.clk, .reset, + wallypipelinedhart hart(.clk, .syntaxerror, .TimerIntM, .ExtIntM, .SwIntM, .MTIME_CLINT, .MTIMECMP_CLINT, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, From d459e3564566177ecbd67fb55577ac1747d51f63 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 7 Dec 2021 13:43:47 -0800 Subject: [PATCH 16/16] undo intentionally breaking commit --- wally-pipelined/src/wally/wallypipelinedsoc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index ed420d9d7..8f3a2234b 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -76,7 +76,7 @@ module wallypipelinedsoc ( synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); // instantiate processor and memories - wallypipelinedhart hart(.clk, .syntaxerror, + wallypipelinedhart hart(.clk, .reset, .TimerIntM, .ExtIntM, .SwIntM, .MTIME_CLINT, .MTIMECMP_CLINT, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,