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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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commit
2cbe179a17
@ -172,8 +172,8 @@ module plic_apb (
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end
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end
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// pending interrupt requests
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// pending interrupt requests
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//assign nextIntPending = (intPending | requests) & ~intInProgress; //
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assign nextIntPending = (intPending | requests) & ~intInProgress; // dh changed back 7/9/22 see if Buildroot still boots. Confirmed to boot successfully.
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assign nextIntPending = requests; // DH: RT made this change May 2022, but it seems to be a bug to not consider intInProgress; see May 23, 2022 slack discussion
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//assign nextIntPending = requests; // DH: RT made this change May 2022, but it seems to be a bug to not consider intInProgress; see May 23, 2022 slack discussion
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flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
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flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
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// context-dependent signals
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// context-dependent signals
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