Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/regression/lint-wally

@@ -7,7 +7,7 @@ verilator=`which verilator`
 basepath=$(dirname $0)/..
 for config in rv64g rv32g; do
     echo "$config linting..."
-    if !($verilator --lint-only --Wall  "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
+    if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
@@ -17,6 +17,5 @@ echo "All lints run with no errors or warnings"
 # --lint-only just runs lint rather than trying to compile and simulate
 # -I points to the include directory where files such as `include wally-config.vh  are found
 
-# For more exhaustive (and sometimes spurious) warnings, run:
+# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
-# verilator --lint-only -Wall -Iconfig/rv64ic src/*
 # Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.

wally-pipelined/src/cache/sram1rw.sv

@@ -14,13 +14,19 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
 );
 
     logic [WIDTH-1:0][DEPTH-1:0] StoredData;
+    logic [$clog2(WIDTH)-1:0] 	 AddrD;
+  
 
     always_ff @(posedge clk) begin
-        ReadData <= StoredData[Addr];
+      AddrD <= Addr;
         if (WriteEnable) begin
             StoredData[Addr] <= #1 WriteData;
         end
     end
+
+      
+  assign ReadData = StoredData[AddrD];
+  
 endmodule
 
 /* verilator lint_on ASSIGNDLY */

wally-pipelined/src/generic/flop/flopenl.sv

@@ -25,14 +25,14 @@
 
 `include "wally-config.vh"
 
-// flop with enable, asynchronous load
+// flop with enable, synchronous load
 module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
   input  logic clk, load, en,
   input  TYPE d,
   input  TYPE val,
   output TYPE q);
 
-  always_ff @(posedge clk, posedge load)
+  always_ff @(posedge clk)
     if (load)    q <= #1 val;
     else if (en) q <= #1 d;
 endmodule

wally-pipelined/src/generic/flop/flopenr.sv

@@ -25,13 +25,13 @@
 
 `include "wally-config.vh"
 
-// flop with enable, asynchronous reset
+// flop with enable, synchronous reset
 module flopenr #(parameter WIDTH = 8) (
   input  logic             clk, reset, en,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
     if (reset)   q <= #1 0;
     else if (en) q <= #1 d;
 endmodule

wally-pipelined/src/generic/flop/flopenrc.sv

@@ -25,13 +25,13 @@
 
 `include "wally-config.vh"
 
-// flop with enable, asynchronous reset, synchronous clear
+// flop with enable, synchronous reset, enabled clear
 module flopenrc #(parameter WIDTH = 8) (
   input  logic             clk, reset, clear, en,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk) 
     if (reset)   q <= #1 0;
     else if (en) 
       if (clear) q <= #1 0;

wally-pipelined/src/generic/flop/flopens.sv

@@ -25,13 +25,13 @@
 
 `include "wally-config.vh"
 
-// flop with enable, asynchronous set
+// flop with enable, synchronous set
 module flopens #(parameter WIDTH = 8) (
   input  logic             clk, set, en,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
-  always_ff @(posedge clk, posedge set)
+  always_ff @(posedge clk) 
     if (set)   q <= #1 1;
     else if (en) q <= #1 d;
 endmodule

wally-pipelined/src/generic/flop/flopr.sv

@@ -25,13 +25,13 @@
 
 `include "wally-config.vh"
 
-// flop with asynchronous reset
+// flop with synchronous reset
 module flopr #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
     if (reset) q <= #1 0;
     else       q <= #1 d;
 endmodule

wally-pipelined/src/generic/flop/floprc.sv

@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-// flop with asynchronous reset, synchronous clear
+// flop with synchronous reset, synchronous clear
 module floprc #(parameter WIDTH = 8) (
   input  logic clk,
   input  logic reset,
@@ -33,9 +33,7 @@ module floprc #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
-    if (reset) q <= #1 0;
+    if (reset | clear ) q <= #1 0;
-    else       
-      if (clear) q <= #1 0;
     else                q <= #1 d;
 endmodule

wally-pipelined/src/generic/flop/synchronizer.sv

@@ -0,0 +1,41 @@
+///////////////////////////////////////////
+// synchronizer.sv
+//
+// Written: David_Harris@hmc.edu 25 October 2021
+// Modified: 
+//
+// Purpose: Two-stage flip-flop synchronizer
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+// ordinary flip-flop
+module synchronizer ( 
+  input  logic clk,
+  input  logic d, 
+  output logic q);
+
+  logic mid;
+
+  always_ff @(posedge clk) begin
+    mid <= #1 d;
+    q <= #1 d;
+  end
+endmodule
+

wally-pipelined/src/wally/wallypipelinedsoc.sv

@@ -32,7 +32,8 @@
 `include "wally-config.vh"
 
 module wallypipelinedsoc (
-  input  logic             clk, reset, 
+  input  logic             clk, reset_ext, 
+  output logic             reset,
   // AHB Lite Interface
   // inputs from external memory
   input  logic [`AHBW-1:0] HRDATAEXT,
@@ -64,6 +65,9 @@ module wallypipelinedsoc (
   logic [3:0]       HSIZED;
   logic             HWRITED;
 
+  // synchronize reset to SOC clock domain
+  synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
+   
   // instantiate processor and memories
   wallypipelinedhart hart(.clk, .reset,
     .TimerIntM, .ExtIntM, .SwIntM, 

wally-pipelined/testbench/testbench.sv

@@ -34,7 +34,7 @@ module testbench;
   parameter TEST="none";
  
   logic        clk;
-  logic        reset;
+  logic        reset_ext, reset;
 
   parameter SIGNATURESIZE = 5000000;
 
@@ -209,7 +209,7 @@ logic [3:0] dummy;
       ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
       $display("Read memfile %s", memfilename);
-      reset = 1; # 42; reset = 0;
+      reset_ext = 1; # 42; reset_ext = 0;
     end
 
   // generate clock to sequence tests
@@ -290,7 +290,7 @@ logic [3:0] dummy;
             ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
             ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
             $display("Read memfile %s", memfilename);
-            reset = 1; # 17; reset = 0;
+            reset_ext = 1; # 47; reset_ext = 0;
         end
       end
     end // always @ (negedge clk)