mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed d cache not honoring StallW for uncache writes and reads.
This commit is contained in:
Ross Thompson
parent
e91501985c
commit
2c946a282f
@ -7,10 +7,10 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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@ -27,14 +27,14 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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@ -306,15 +306,10 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
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add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/ReadDataW
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/StallW
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/LSUStall
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add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
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add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
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add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
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add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
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@ -328,34 +323,34 @@ add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
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add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
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add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
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@ -370,12 +365,12 @@ add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/
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add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF
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add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM
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add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM
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add wave -noupdate -expand -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState
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add wave -noupdate -expand -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW
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add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate
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add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead
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add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr
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add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE
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add wave -noupdate -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState
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add wave -noupdate -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW
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add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate
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add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead
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add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr
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add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE
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add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
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@ -399,18 +394,14 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
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add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate /testbench/dut/uncore/dtim/HWADDR
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add wave -noupdate /testbench/dut/uncore/dtim/A
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add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
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add wave -noupdate /testbench/dut/uncore/dtim/memwrite
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add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
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add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HCLK
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add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
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add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HADDR
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add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
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add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 12} {718836 ns} 0} {{Cursor 4} {8790617 ns} 0}
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WaveRestoreCursors {{Cursor 12} {4076 ns} 0} {{Cursor 4} {8790617 ns} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 297
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@ -426,4 +417,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {718645 ns} {719057 ns}
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WaveRestoreZoom {4026 ns} {4254 ns}
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95
wally-pipelined/src/cache/dcache.sv
vendored
95
wally-pipelined/src/cache/dcache.sv
vendored
@ -51,6 +51,7 @@ module dcache
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input logic PendingInterruptM,
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input logic DTLBMissM,
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input logic CacheableM,
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input logic DTLBWriteM,
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// ahb side
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output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
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output logic AHBRead,
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@ -133,6 +134,7 @@ module dcache
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typedef enum {STATE_READY,
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STATE_MISS_FETCH_WDV,
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STATE_MISS_FETCH_DONE,
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STATE_MISS_EVICT_DIRTY,
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@ -141,6 +143,7 @@ module dcache
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STATE_MISS_READ_WORD,
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STATE_MISS_READ_WORD_DELAY,
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STATE_MISS_WRITE_WORD,
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STATE_AMO_MISS_FETCH_WDV,
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STATE_AMO_MISS_FETCH_DONE,
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STATE_AMO_MISS_CHECK_EVICTED_DIRTY,
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@ -151,17 +154,19 @@ module dcache
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STATE_AMO_MISS_WRITE_WORD,
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STATE_AMO_UPDATE,
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STATE_AMO_WRITE,
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STATE_PTW_READY,
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STATE_PTW_MISS_FETCH_WDV,
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STATE_PTW_MISS_FETCH_DONE,
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STATE_PTW_MISS_CHECK_EVICTED_DIRTY,
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STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_PTW_MISS_WRITE_CACHE_BLOCK,
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STATE_PTW_MISS_READ_SRAM,
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STATE_PTW_READ_MISS_FETCH_WDV,
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STATE_PTW_READ_MISS_FETCH_DONE,
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STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
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STATE_PTW_READ_MISS_READ_WORD,
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STATE_PTW_READ_MISS_READ_WORD_DELAY,
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STATE_UNCACHED_WRITE,
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STATE_UNCACHED_WRITE_DONE,
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STATE_UNCACHED_READ,
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STATE_UNCACHED_READ_DONE,
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STATE_CPU_BUSY} statetype;
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statetype CurrState, NextState;
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@ -420,7 +425,7 @@ module dcache
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STATE_READY: begin
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// TLB Miss
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if(AnyCPUReqM & DTLBMissM) begin
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NextState = STATE_PTW_MISS_FETCH_WDV;
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NextState = STATE_PTW_READY;
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end
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// amo hit
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else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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@ -428,11 +433,10 @@ module dcache
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DCacheStall = 1'b1;
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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else NextState = STATE_AMO_UPDATE;
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end
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// read hit valid cached
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else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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NextState = STATE_READY;
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DCacheStall = 1'b0;
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||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
@ -562,14 +566,69 @@ module dcache
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_MISS_FETCH_WDV: begin
|
||||
STATE_PTW_READY: begin
|
||||
CommittedM = 1'b1;
|
||||
// return to ready if page table walk completed.
|
||||
if(DTLBWriteM) begin
|
||||
NextState = STATE_READY;
|
||||
|
||||
// read hit valid cached
|
||||
end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
|
||||
NextState = STATE_PTW_READY;
|
||||
DCacheStall = 1'b0;
|
||||
end
|
||||
|
||||
// read miss valid cached
|
||||
else if((MemRWM[1]) & CacheableM & ~ExceptionM & ~CacheHit) begin
|
||||
NextState = STATE_PTW_READ_MISS_FETCH_WDV;
|
||||
CntReset = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_FETCH_WDV: begin
|
||||
DCacheStall = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
AHBRead = 1'b1;
|
||||
SelAdrM = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
|
||||
if (FetchCountFlag & AHBAck) begin
|
||||
NextState = STATE_PTW_READ_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_PTW_READ_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_FETCH_DONE: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 1'b1;
|
||||
if (FetchCountFlag & AHBAck) begin
|
||||
NextState = STATE_PTW_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_PTW_MISS_FETCH_WDV;
|
||||
end
|
||||
CntReset = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin
|
||||
SRAMBlockWriteEnableM = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
NextState = STATE_PTW_READ_MISS_READ_WORD;
|
||||
SelAdrM = 1'b1;
|
||||
SetValidM = 1'b1;
|
||||
ClearDirtyM = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_READ_WORD: begin
|
||||
SelAdrM = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_READ_WORD_DELAY: begin
|
||||
SelAdrM = 1'b1;
|
||||
NextState = STATE_PTW_READY;
|
||||
CommittedM = 1'b1;
|
||||
end
|
||||
|
||||
STATE_CPU_BUSY : begin
|
||||
@ -601,13 +660,15 @@ module dcache
|
||||
|
||||
STATE_UNCACHED_WRITE_DONE: begin
|
||||
CommittedM = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
STATE_UNCACHED_READ_DONE: begin
|
||||
CommittedM = 1'b1;
|
||||
SelUncached = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
default: begin
|
||||
|
||||
@ -333,6 +333,7 @@ module lsu
|
||||
.PendingInterruptM(PendingInterruptMtoDCache),
|
||||
.DTLBMissM(DTLBMissM),
|
||||
.CacheableM(CacheableM),
|
||||
.DTLBWriteM(DTLBWriteM),
|
||||
|
||||
// AHB connection
|
||||
.AHBPAdr(DCtoAHBPAdrM),
|
||||
|
||||
@ -544,9 +544,9 @@ string tests32f[] = '{
|
||||
else tests = {tests, tests64iNOc};
|
||||
if (`M_SUPPORTED) tests = {tests, tests64m};
|
||||
//if (`A_SUPPORTED) tests = {tests, tests64a};
|
||||
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
||||
if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||
if (`MEM_VIRTMEM) tests = {tests64periph, tests64mmu, tests};
|
||||
end
|
||||
//tests = {tests64a, tests};
|
||||
end else begin // RV32
|
||||
|
||||
Loading…
Reference in New Issue
Block a user