From 2c4682c4bec385f3a96e76fb97d27d73a8f2289f Mon Sep 17 00:00:00 2001
From: Thomas Fleming <tfleming@hmc.edu>
Date: Thu, 15 Apr 2021 14:48:39 -0400
Subject: [PATCH] Connect tlb and icache properly

---
 wally-pipelined/src/ifu/ifu.sv | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index bc0443002..d5ecf470e 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -74,14 +74,13 @@ module ifu (
   logic             CompressedF;
   logic [31:0]      InstrRawD, InstrE, InstrW;
   logic [31:0]      nop = 32'h00000013; // instruction for NOP
-  logic [`XLEN-1:0] ITLBInstrPAdrF, ICacheInstrPAdrF;
   // *** send this to the trap unit
   logic             ITLBPageFaultF;
 
   tlb #(3) itlb(.TLBAccess(1'b1), .VirtualAddress(PCF),
                 .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),
                 .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
-                .PhysicalAddress(ITLBInstrPAdrF), .TLBMiss(ITLBMissF),
+                .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
                 .TLBHit(ITLBHitF), .TLBPageFault(ITLBPageFaultF),
                 .*);
 
@@ -97,15 +96,11 @@ module ifu (
   // assign InstrReadF = 1; // *** & ICacheMissF; add later
 
   // jarred 2021-03-14 Add instrution cache block to remove rd2
-  assign PCPF = PCF; // Temporary workaround until iTLB is live
   icache ic(
     .*,
-    .InstrPAdrF(ICacheInstrPAdrF),
     .UpperPCPF(PCPF[`XLEN-1:12]),
     .LowerPCF(PCF[11:0])
   );
-  // Prioritize the iTLB for reads if it wants one
-  mux2 #(`XLEN) instrPAdrMux(ICacheInstrPAdrF, ITLBInstrPAdrF, ITLBMissF, InstrPAdrF);
 
   assign PrivilegedChangePCM = RetM | TrapM;