From 2c2c1b52215201439e46fc82e3abcd88cdbdd4f0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 20 Feb 2023 18:45:45 -0600 Subject: [PATCH] Cleanup branch predictor files. --- src/ifu/bpred/foldedgshare.sv | 146 --------------- src/ifu/bpred/globalhistory.sv | 80 -------- src/ifu/bpred/gshare.sv | 13 +- src/ifu/bpred/gsharebasic.sv | 11 +- src/ifu/bpred/optgshare.sv | 219 ---------------------- src/ifu/bpred/speculativeglobalhistory.sv | 136 -------------- src/ifu/bpred/speculativegshare.sv | 137 -------------- 7 files changed, 13 insertions(+), 729 deletions(-) delete mode 100644 src/ifu/bpred/foldedgshare.sv delete mode 100644 src/ifu/bpred/globalhistory.sv delete mode 100644 src/ifu/bpred/optgshare.sv delete mode 100644 src/ifu/bpred/speculativeglobalhistory.sv delete mode 100644 src/ifu/bpred/speculativegshare.sv diff --git a/src/ifu/bpred/foldedgshare.sv b/src/ifu/bpred/foldedgshare.sv deleted file mode 100644 index 85b7db383..000000000 --- a/src/ifu/bpred/foldedgshare.sv +++ /dev/null @@ -1,146 +0,0 @@ -/////////////////////////////////////////// -// gsharePredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module foldedgshare #(parameter k = 16, depth = 10) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, -// input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic PCSrcE -); - - logic MatchF, MatchD, MatchE, MatchM, MatchW; - logic MatchNextX, MatchXF; - - logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW; - - logic [k-1:0] GHRF; - logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW; - logic [k-1:0] IndexNextF, IndexF; - logic [k-1:0] IndexD, IndexE, IndexM, IndexW; - logic [depth-1:0] FinalIndexNextF, FinalIndexW; - - logic PCSrcM, PCSrcW; - logic [`XLEN-1:0] PCW; - - logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - localparam delta = 2 * depth - k; - - assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; - assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]}; - assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; - assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; - assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]}; - - // just be dumb for now. - //localparam int kToDepthRatio = (k+depth) / depth; - assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]}; - assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]}; - - ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), - .ra1(FinalIndexNextF), - .rd1(TableDirPredictionF), - .wa2(FinalIndexW), - .wd2(NewDirPredictionW), - .we2(BranchInstrW & ~StallW & ~FlushW), - .bwe2(1'b1)); - - // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage - // and then register for use in the Fetch stage. - assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); - assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); - assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); - assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM); - assign MatchW = BranchInstrW & (IndexNextF == IndexW); - assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW; - - flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - - assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : - MatchD ? NewDirPredictionD : - MatchE ? NewDirPredictionE : - MatchM ? NewDirPredictionM : - NewDirPredictionW; - - flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); - - assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - // New prediction pipeline - satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF)); - flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM); - flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW); - - // PCSrc pipeline - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW); - - // GHR pipeline - assign GHRNextF = FlushD ? GHRNextD[k:1] : - BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - GHRF; - - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - - assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF}; - flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - - assign GHRNextE = FlushE ? GHRNextM : GHRD; - flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); - assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; - - assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); - - assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); - -endmodule diff --git a/src/ifu/bpred/globalhistory.sv b/src/ifu/bpred/globalhistory.sv deleted file mode 100644 index a88804773..000000000 --- a/src/ifu/bpred/globalhistory.sv +++ /dev/null @@ -1,80 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module globalhistory #(parameter k = 10) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic BranchInstrE, BranchInstrM, PCSrcE -); - - logic [k-1:0] IndexNextF, IndexE; - logic [1:0] DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE, NewDirPredictionM; - - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; - logic [k-1:0] GHRNext; - logic PCSrcM; - - assign IndexNextF = GHR; - assign IndexE = GHRM; - - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF), .ce2(~StallM & ~FlushM), - .ra1(IndexNextF), - .rd1(DirPredictionF), - .wa2(IndexE), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallW & ~FlushW), - .bwe2(1'b1)); - - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, DirPredictionD, DirPredictionE); - - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - - assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR; - flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR); - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - - flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); - flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); - flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); - - -endmodule diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index bb9d25f49..c13bce943 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -1,12 +1,13 @@ /////////////////////////////////////////// -// globalHistoryPredictor.sv +// gshare.sv // -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: +// Written: Ross Thompson +// Email: ross1728@gmail.com +// Created: 16 March 2021 +// Adapted from ssanghai@hmc.edu (Shreya Sanghai) +// Modified: 20 February 2023 // -// Purpose: Global History Branch predictor with parameterized global history register +// Purpose: gshare and Global History Branch predictors // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 45438b856..d73797275 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -1,10 +1,11 @@ /////////////////////////////////////////// -// globalHistoryPredictor.sv +// gsharebasic.sv // -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: +// Written: Ross Thompson +// Email: ross1728@gmail.com +// Created: 16 March 2021 +// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation. +// Modified: 20 February 2023 // // Purpose: Global History Branch predictor with parameterized global history register // diff --git a/src/ifu/bpred/optgshare.sv b/src/ifu/bpred/optgshare.sv deleted file mode 100644 index 78c98c5e6..000000000 --- a/src/ifu/bpred/optgshare.sv +++ /dev/null @@ -1,219 +0,0 @@ -/////////////////////////////////////////// -// gsharePredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module optgshare #(parameter k = 10) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, -// input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic PCSrcE -); - - logic MatchF, MatchD, MatchE, MatchM, MatchW; - logic MatchNextX, MatchXF; - - logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW; - - logic [k-1:0] GHRF; - logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW; - logic [k-1:0] IndexNextF, IndexF; - logic [k-1:0] IndexD, IndexE, IndexM, IndexW; - - logic PCSrcM, PCSrcW; - logic [`XLEN-1:0] PCW; - - logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - - logic [k+4:0] GHRNext, GHR; - logic GHRUpdateEn; - - assign GHRUpdateEn = BranchInstrF | (DirPredictionWrongE & BranchInstrE) | - FlushD | FlushE | FlushM | FlushW; - - // it doesn't work this way. Instead we need to see how many branch instructions are flushed. - // then shift over by that amount. - logic RemoveBrW, RemoveBrM, RemoveBrE, RemoveBrD, RemoveBrF, RemoveBrNextF; - - assign RemoveBrW = '0; - assign RemoveBrM = BranchInstrM & FlushW; - assign RemoveBrE = BranchInstrE & FlushM; - assign RemoveBrD = BranchInstrD & FlushE; - assign RemoveBrF = BranchInstrF & FlushD; - assign RemoveBrNextF = BranchInstrF & FlushD; - - always_comb begin - casez ({BranchInstrF, DirPredictionWrongE, RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM}) - 6'b00_0000: GHRNext = GHR; // no change - 6'b00_0001: GHRNext = {GHR[k+4:k+1], GHR[k-1:0], 1'b0}; // RemoveBrM - 6'b0?_0010: GHRNext = {GHR[k+4:k+2], GHR[k:0], 1'b0}; // RemoveBrE - 6'b0?_0011: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrE, RemoveBrM - - 6'b00_0100: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrD - 6'b00_0101: GHRNext = {GHR[k+4:k+3], GHR[k+1:0], 1'b0}; // RemoveBrD, RemoveBrM - 6'b0?_0110: GHRNext = {GHR[k+4:k+3], GHR[k+1], GHR[k-1:0], 2'b0}; // RemoveBrD, RemoveBrE - 6'b0?_0111: GHRNext = {GHR[k+4:k+3], GHR[k-1:0], 3'b0}; // RemoveBrD, RemoveBrE, RemoveBrM - - 6'b?0_1000: GHRNext = {GHR[k+2:0], 2'b0}; // RemoveBrF, - 6'b?0_1001: GHRNext = {GHR[k+2:k+1], GHR[k-1:0], 3'b0}; // RemoveBrF, RemoveBrM - 6'b??_1010: GHRNext = {GHR[k+2], GHR[k:0], 3'b0}; // RemoveBrF, RemoveBrE - 6'b??_1011: GHRNext = {GHR[k+2], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrE, RemoveBrM - - 6'b?0_1100: GHRNext = {GHR[k+1:0], 3'b0}; // RemoveBrF, RemoveBrD - 6'b?0_1101: GHRNext = {GHR[k+1], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrM - 6'b??_1110: GHRNext = {GHR[k:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrE - 6'b??_1111: GHRNext = {GHR[k-1:0], 5'b0}; // RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM - - 6'b?1_0000: GHRNext = {PCSrcE, GHR[k+3:0]}; // Miss prediction, no branches to flushes - 6'b?1_0001: GHRNext = {PCSrcE, GHR[k+3:k], GHR[k-1:1], 1'b0}; // Miss prediction, branch in Memory stage dropped - - 6'b?1_1100: GHRNext = {PCSrcE, GHR[k+1:0], 2'b00}; // Miss prediction, cannot have RemoveBrE - 6'b?1_1101: GHRNext = {PCSrcE, GHR[k+1], GHR[k-1:0], 3'b0}; // Miss prediction, cannot have RemoveBrE - 6'b10_0000: GHRNext = {DirPredictionF[1], GHR[k+4:1]}; - 6'b10_0001: GHRNext = {DirPredictionF[1], GHR[k+4:k+1], GHR[k-1:1], 1'b0}; - 6'b10_0010: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k:1], 1'b0}; - 6'b10_0011: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k-1:1], 2'b0}; - 6'b10_0100: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1:1], 1'b0}; - 6'b10_0101: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1], GHR[k-1:1], 2'b0}; - 6'b10_0110: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k], GHR[k-1:1], 2'b0}; - 6'b10_0111: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k-1:1], 3'b0}; - - default: GHRNext = GHR; - endcase - end - - flopenr #(k+5) GHRReg(clk, reset, GHRUpdateEn, GHRNext, GHR); - logic [k-1:0] GHRNextF_temp, GHRF_temp; - logic [k:0] GHRD_temp, GHRE_temp, GHRM_temp, GHRW_temp; - logic GHRFExtra_temp; - - // these are also in the ieu controller. should create inputs. - logic InstrValidF, InstrValidD, InstrValidE, InstrValidM, InstrValidW; - flopenrc #(1) InstrValidFReg(clk, reset, FlushD, ~StallF, 1'b1, InstrValidF); - flopenrc #(1) InstrValidDReg(clk, reset, FlushD, ~StallD, InstrValidF, InstrValidD); - flopenrc #(1) InstrValidEReg(clk, reset, FlushE, ~StallE, InstrValidD, InstrValidE); - flopenrc #(1) InstrValidMReg(clk, reset, FlushM, ~StallM, InstrValidE, InstrValidM); - flopenrc #(1) InstrValidWReg(clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW); - - - assign GHRNextF_temp = GHRNext[k+4:5]; - assign GHRF_temp = InstrValidF ? GHR[k+3:4] : GHRNextF_temp; - assign GHRFExtra_temp = InstrValidF ? 1'b0 : GHR[k+4]; - assign GHRD_temp = InstrValidD ? GHR[k+3:3] : {GHRFExtra_temp, GHRF_temp}; - assign GHRE_temp = InstrValidE ? GHR[k+2:2] : GHRD_temp; - assign GHRM_temp = InstrValidM ? GHR[k+1:1] : GHRE_temp; - assign GHRW_temp = InstrValidW ? GHR[k:0] : GHRM_temp; - - - assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; - assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]}; - assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; - assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; - assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]}; - - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), - .ra1(IndexNextF), - .rd1(TableDirPredictionF), - .wa2(IndexW), - .wd2(NewDirPredictionW), - .we2(BranchInstrW & ~StallW & ~FlushW), - .bwe2(1'b1)); - - // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage - // and then register for use in the Fetch stage. - assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); - assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); - assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); - assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM); - assign MatchW = BranchInstrW & (IndexNextF == IndexW); - assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW; - - flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - - assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : - MatchD ? NewDirPredictionD : - MatchE ? NewDirPredictionE : - MatchM ? NewDirPredictionM : - NewDirPredictionW; - - flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); - - assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - // New prediction pipeline - satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF)); - flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM); - flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW); - - // PCSrc pipeline - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW); - - // GHR pipeline - assign GHRNextF = FlushD ? GHRNextD[k:1] : - BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - GHRF; - - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - - assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF}; - flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - - assign GHRNextE = FlushE ? GHRNextM : GHRD; - flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); - assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; - - assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); - - assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); - -endmodule diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv deleted file mode 100644 index ca36a19f1..000000000 --- a/src/ifu/bpred/speculativeglobalhistory.sv +++ /dev/null @@ -1,136 +0,0 @@ -/////////////////////////////////////////// -// speculativeglobalhistory.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module speculativeglobalhistory #(parameter int k = 10 ) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [3:0] PredInstrClassF, - input logic [3:0] InstrClassD, InstrClassE, InstrClassM, - input logic [3:0] WrongPredInstrClassD, - input logic PCSrcE -); - - logic MatchF, MatchD, MatchE; - logic MatchNextX, MatchXF; - - logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE; - - logic [k-1:0] GHRF, GHRD, GHRE, GHRM; - logic GHRLastF; - logic [k-1:0] GHRNextF, GHRNextD, GHRNextE, GHRNextM; - logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE; - logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - - logic FlushDOrDirWrong; - - assign IndexNextF = GHRNextF; - assign IndexF = GHRF ; - assign IndexD = GHRD[k-1:0] ; - assign IndexE = GHRE[k-1:0] ; - - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), - .ra1(IndexNextF), - .rd1(TableDirPredictionF), - .wa2(IndexE), - .wd2(NewDirPredictionE), - .we2(InstrClassE[0]), - .bwe2(1'b1)); - - // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage - // and then register for use in the Fetch stage. - assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF); - assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD); - assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE); - assign MatchNextX = MatchF | MatchD | MatchE; - - flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - - assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} : - MatchD ? {2{DirPredictionD[1]}} : - NewDirPredictionE ; - - flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); - - assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - - // GHR pipeline - - // If Fetch has a branch, speculatively insert prediction into the GHR - // If the front end is flushed or the direction prediction is wrong, reset to - // most recent valid GHR. For a BP wrong this is GHRD with the correct prediction shifted in. - // For FlushE this is GHRE. GHRNextE is both. - logic [k-1:0] GHRClassWrongAndPredF; - logic [k-1:0] GHRClassWrong; - mux2 #(k) GHRClassWrongAndPredFMux({DirPredictionF[1], DirPredictionD[1], GHRF[k-1:2]}, {DirPredictionF[1], GHRF[k-2:0]}, ~InstrClassD[0], GHRClassWrongAndPredF); - - assign FlushDOrDirWrong = FlushD | DirPredictionWrongE; -// mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], -// {FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF); - - mux5 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRClassWrong, GHRClassWrongAndPredF, GHRNextE[k-1:0], - {FlushDOrDirWrong, WrongPredInstrClassD[0], PredInstrClassF[0]}, GHRNextF); - - // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift. - flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF); - flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF); - - // With instruction class prediction, the class could be wrong and is checked in Decode. - // If it is wrong and branch does exist then shift right and insert the prediction. - // If the branch does not exist then shift left and use GHRLastF to restore the LSB. - mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong); - // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. - mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); - - flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD); - - mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); - - flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); - - assign GHRNextM = FlushM ? GHRM : GHRE; - flopenr #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; - -endmodule diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv deleted file mode 100644 index 48601021a..000000000 --- a/src/ifu/bpred/speculativegshare.sv +++ /dev/null @@ -1,137 +0,0 @@ -/////////////////////////////////////////// -// gsharePredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module speculativegshare #(parameter int k = 10 ) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, - input logic [3:0] PredInstrClassF, - input logic [3:0] InstrClassD, InstrClassE, InstrClassM, - input logic [3:0] WrongPredInstrClassD, - input logic PCSrcE -); - - logic MatchF, MatchD, MatchE; - logic MatchNextX, MatchXF; - - logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE; - - logic [k-1:0] GHRF, GHRD, GHRE, GHRM; - logic GHRLastF; - logic [k-1:0] GHRNextF, GHRNextD, GHRNextE, GHRNextM; - logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE; - logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - - logic FlushDOrDirWrong; - - assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; - assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]}; - assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; - - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), - .ra1(IndexNextF), - .rd1(TableDirPredictionF), - .wa2(IndexE), - .wd2(NewDirPredictionE), - .we2(InstrClassE[0]), - .bwe2(1'b1)); - - // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage - // and then register for use in the Fetch stage. - assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF); - assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD); - assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE); - assign MatchNextX = MatchF | MatchD | MatchE; - - flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - - assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} : - MatchD ? {2{DirPredictionD[1]}} : - NewDirPredictionE ; - - flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); - - assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - - // GHR pipeline - - // If Fetch has a branch, speculatively insert prediction into the GHR - // If the front end is flushed or the direction prediction is wrong, reset to - // most recent valid GHR. For a BP wrong this is GHRD with the correct prediction shifted in. - // For FlushE this is GHRE. GHRNextE is both. - logic [k-1:0] GHRClassWrongAndPredF; - logic [k-1:0] GHRClassWrong; - mux2 #(k) GHRClassWrongAndPredFMux({DirPredictionF[1], DirPredictionD[1], GHRF[k-1:2]}, {DirPredictionF[1], GHRF[k-2:0]}, ~InstrClassD[0], GHRClassWrongAndPredF); - - assign FlushDOrDirWrong = FlushD | DirPredictionWrongE; -// mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], -// {FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF); - - mux5 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRClassWrong, GHRClassWrongAndPredF, GHRNextE[k-1:0], - {FlushDOrDirWrong, WrongPredInstrClassD[0], PredInstrClassF[0]}, GHRNextF); - - // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift. - flopenr #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF); - flopenr #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF); - - // With instruction class prediction, the class could be wrong and is checked in Decode. - // If it is wrong and branch does exist then shift right and insert the prediction. - // If the branch does not exist then shift left and use GHRLastF to restore the LSB. - mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong); - // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE. - mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD); - - flopenr #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD); - - mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE); - - flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); - - assign GHRNextM = FlushM ? GHRM : GHRE; - flopenr #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; - -endmodule