From 4639e92fda9ae60031476f5b4c59c79da8137a32 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 3 May 2024 08:56:14 -0700 Subject: [PATCH 1/3] Turned off BMUSubArith for bext/bexti --- src/ieu/bmu/bmuctrl.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 887ac0065..4f0a28324 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -136,14 +136,14 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( if (P.ZBS_SUPPORTED) begin // ZBS casez({OpD, Funct7D, Funct3D}) 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_1_0_0_1_0_0; // bext 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_0_0_1_0_0_1_0_0; // binv 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_0_0_1_0_0_1_0_0; // bset endcase if (P.XLEN==32) // ZBS 64-bit casez({OpD, Funct7D, Funct3D}) 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0; // bexti + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_0_0_1_0_0; // bexti 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti endcase From 4d5ac3b8692077128b515fd31eeac540cc9ea7ec Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 3 May 2024 08:59:40 -0700 Subject: [PATCH 2/3] Turned off BMUSubArith for bext/bexti --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4f0a28324..62376865f 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -150,7 +150,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( else if (P.XLEN==64) // ZBS 64-bit casez({OpD, Funct7D, Funct3D}) 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0; // bexti (rv64) + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_0_0_1_0_0; // bexti (rv64) 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi (rv64) 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti (rv64) endcase From bdc2ad494fc47bd4acb7c69afa1ed50a47e0e0c8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 3 May 2024 09:07:33 -0700 Subject: [PATCH 3/3] Shared AND gate in ALU for extract / and paths --- src/ieu/alu.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 0b19e5757..783d39495 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -50,6 +50,7 @@ module alu import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] CondMaskB; // Result of B mask select mux logic [P.XLEN-1:0] CondShiftA; // Result of A shifted select mux logic [P.XLEN-1:0] ZeroCondMaskInvB; // B input to AND gate, accounting for czero.* instructions + logic [P.XLEN-1:0] AndResult; // AND result logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic Asign, Bsign; // Sign bits of A, B @@ -72,6 +73,7 @@ module alu import cvw::*; #(parameter cvw_t P) ( assign Bsign = B[P.XLEN-1]; assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; assign LTU = ~Carry; + assign AndResult = A & ZeroCondMaskInvB; // Select appropriate ALU Result always_comb @@ -81,9 +83,10 @@ module alu import cvw::*; #(parameter cvw_t P) ( 3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv - 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported) +// 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskInvB)}} : Shift; // bext (or IEU shift when BMU not supported) + 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(AndResult)}} : Shift; // bext (or IEU shift when BMU not supported) 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset - 3'b111: FullResult = A & ZeroCondMaskInvB; // and, bclr, czero.* + 3'b111: FullResult = AndResult; // and, bclr, czero.* endcase // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits