From 2b9e5608a451faab9a24849d8016475ef327aba5 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 6 Apr 2023 16:01:58 -0500 Subject: [PATCH] Build doesn't work. AXI Crossbar has problems. --- fpga/constraints/debug2.xdc | 193 +----- fpga/src/fpgaTop.v | 84 +-- .../src/uncore/newsdc/axi_sdc_controller.v | 40 +- src/generic/mem/rom1p1r.sv | 646 +++++++++++++++++- src/uncore/uncore.sv | 10 +- src/wally/wallypipelinedsoc.sv | 4 +- tests/custom/boot/Makefile | 4 +- tests/custom/boot/boot.c | 18 +- tests/custom/boot/boot.h | 5 +- 9 files changed, 773 insertions(+), 231 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 71e45611e..13733e579 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -926,212 +926,93 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe173] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]] - +# ============== AXI SDC STUFF ================ create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe174] +set_property port_width 1 [get_debug_ports u_ila_0/probe174] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] -connect_debug_port u_ila_0/probe174 [get_nets [list {BUS_axi_awid[0]} {BUS_axi_awid[1]} {BUS_axi_awid[2]} {BUS_axi_awid[3]} ]] - +connect_debug_port u_ila_0/probe174 [get_nets [list {axiSDC/clock_posedge}]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe175] +set_property port_width 32 [get_debug_ports u_ila_0/probe175] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] -connect_debug_port u_ila_0/probe175 [get_nets [list {BUS_axi_awlen[0]} {BUS_axi_awlen[1]} {BUS_axi_awlen[2]} {BUS_axi_awlen[3]} {BUS_axi_awlen[4]} {BUS_axi_awlen[5]} {BUS_axi_awlen[6]} {BUS_axi_awlen[7]} ]] - +connect_debug_port u_ila_0/probe175 [get_nets [list {axiSDC/argument_reg[0]} {axiSDC/argument_reg[1]} {axiSDC/argument_reg[2]} {axiSDC/argument_reg[3]} {axiSDC/argument_reg[4]} {axiSDC/argument_reg[5]} {axiSDC/argument_reg[6]} {axiSDC/argument_reg[7]} {axiSDC/argument_reg[8]} {axiSDC/argument_reg[9]} {axiSDC/argument_reg[10]} {axiSDC/argument_reg[11]} {axiSDC/argument_reg[12]} {axiSDC/argument_reg[13]} {axiSDC/argument_reg[14]} {axiSDC/argument_reg[15]} {axiSDC/argument_reg[16]} {axiSDC/argument_reg[17]} {axiSDC/argument_reg[18]} {axiSDC/argument_reg[19]} {axiSDC/argument_reg[20]} {axiSDC/argument_reg[21]} {axiSDC/argument_reg[22]} {axiSDC/argument_reg[23]} {axiSDC/argument_reg[24]} {axiSDC/argument_reg[25]} {axiSDC/argument_reg[26]} {axiSDC/argument_reg[27]} {axiSDC/argument_reg[28]} {axiSDC/argument_reg[29]} {axiSDC/argument_reg[30]} {axiSDC/argument_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe176] +set_property port_width 25 [get_debug_ports u_ila_0/probe176] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] -connect_debug_port u_ila_0/probe176 [get_nets [list {BUS_axi_awsize[0]} {BUS_axi_awsize[1]} {BUS_axi_awsize[2]} ]] - +connect_debug_port u_ila_0/probe176 [get_nets [list {axiSDC/cmd_timeout_reg[0]} {axiSDC/cmd_timeout_reg[1]} {axiSDC/cmd_timeout_reg[2]} {axiSDC/cmd_timeout_reg[3]} {axiSDC/cmd_timeout_reg[4]} {axiSDC/cmd_timeout_reg[5]} {axiSDC/cmd_timeout_reg[6]} {axiSDC/cmd_timeout_reg[7]} {axiSDC/cmd_timeout_reg[8]} {axiSDC/cmd_timeout_reg[9]} {axiSDC/cmd_timeout_reg[10]} {axiSDC/cmd_timeout_reg[11]} {axiSDC/cmd_timeout_reg[12]} {axiSDC/cmd_timeout_reg[13]} {axiSDC/cmd_timeout_reg[14]} {axiSDC/cmd_timeout_reg[15]} {axiSDC/cmd_timeout_reg[16]} {axiSDC/cmd_timeout_reg[17]} {axiSDC/cmd_timeout_reg[18]} {axiSDC/cmd_timeout_reg[19]} {axiSDC/cmd_timeout_reg[20]} {axiSDC/cmd_timeout_reg[21]} {axiSDC/cmd_timeout_reg[22]} {axiSDC/cmd_timeout_reg[23]} {axiSDC/cmd_timeout_reg[24]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe177] +set_property port_width 28 [get_debug_ports u_ila_0/probe177] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] -connect_debug_port u_ila_0/probe177 [get_nets [list {BUS_axi_awburst[0]} {BUS_axi_awburst[1]} ]] - +connect_debug_port u_ila_0/probe177 [get_nets [list {axiSDC/data_timeout_reg[0]} {axiSDC/data_timeout_reg[1]} {axiSDC/data_timeout_reg[2]} {axiSDC/data_timeout_reg[3]} {axiSDC/data_timeout_reg[4]} {axiSDC/data_timeout_reg[5]} {axiSDC/data_timeout_reg[6]} {axiSDC/data_timeout_reg[7]} {axiSDC/data_timeout_reg[8]} {axiSDC/data_timeout_reg[9]} {axiSDC/data_timeout_reg[10]} {axiSDC/data_timeout_reg[11]} {axiSDC/data_timeout_reg[12]} {axiSDC/data_timeout_reg[13]} {axiSDC/data_timeout_reg[14]} {axiSDC/data_timeout_reg[15]} {axiSDC/data_timeout_reg[16]} {axiSDC/data_timeout_reg[17]} {axiSDC/data_timeout_reg[18]} {axiSDC/data_timeout_reg[19]} {axiSDC/data_timeout_reg[20]} {axiSDC/data_timeout_reg[21]} {axiSDC/data_timeout_reg[22]} {axiSDC/data_timeout_reg[23]} {axiSDC/data_timeout_reg[24]} {axiSDC/data_timeout_reg[25]} {axiSDC/data_timeout_reg[26]} {axiSDC/data_timeout_reg[27]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe178] +set_property port_width 1 [get_debug_ports u_ila_0/probe178] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] -connect_debug_port u_ila_0/probe178 [get_nets [list {BUS_axi_awcache[0]} {BUS_axi_awcache[1]} {BUS_axi_awcache[2]} {BUS_axi_awcache[3]} ]] - +connect_debug_port u_ila_0/probe178 [get_nets [list {axiSDC/software_reset_reg}]] create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe179] +set_property port_width 32 [get_debug_ports u_ila_0/probe179] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] -connect_debug_port u_ila_0/probe179 [get_nets [list {BUS_axi_awaddr[0]} {BUS_axi_awaddr[1]} {BUS_axi_awaddr[2]} {BUS_axi_awaddr[3]} {BUS_axi_awaddr[4]} {BUS_axi_awaddr[5]} {BUS_axi_awaddr[6]} {BUS_axi_awaddr[7]} {BUS_axi_awaddr[8]} {BUS_axi_awaddr[9]} {BUS_axi_awaddr[10]} {BUS_axi_awaddr[11]} {BUS_axi_awaddr[12]} {BUS_axi_awaddr[13]} {BUS_axi_awaddr[14]} {BUS_axi_awaddr[15]} {BUS_axi_awaddr[16]} {BUS_axi_awaddr[17]} {BUS_axi_awaddr[18]} {BUS_axi_awaddr[19]} {BUS_axi_awaddr[20]} {BUS_axi_awaddr[21]} {BUS_axi_awaddr[22]} {BUS_axi_awaddr[23]} {BUS_axi_awaddr[24]} {BUS_axi_awaddr[25]} {BUS_axi_awaddr[26]} {BUS_axi_awaddr[27]} {BUS_axi_awaddr[28]} {BUS_axi_awaddr[29]} {BUS_axi_awaddr[30]} ]] - +connect_debug_port u_ila_0/probe179 [get_nets [list {axiSDC/response_0_reg[0]} {axiSDC/response_0_reg[1]} {axiSDC/response_0_reg[2]} {axiSDC/response_0_reg[3]} {axiSDC/response_0_reg[4]} {axiSDC/response_0_reg[5]} {axiSDC/response_0_reg[6]} {axiSDC/response_0_reg[7]} {axiSDC/response_0_reg[8]} {axiSDC/response_0_reg[9]} {axiSDC/response_0_reg[10]} {axiSDC/response_0_reg[11]} {axiSDC/response_0_reg[12]} {axiSDC/response_0_reg[13]} {axiSDC/response_0_reg[14]} {axiSDC/response_0_reg[15]} {axiSDC/response_0_reg[16]} {axiSDC/response_0_reg[17]} {axiSDC/response_0_reg[18]} {axiSDC/response_0_reg[19]} {axiSDC/response_0_reg[20]} {axiSDC/response_0_reg[21]} {axiSDC/response_0_reg[22]} {axiSDC/response_0_reg[23]} {axiSDC/response_0_reg[24]} {axiSDC/response_0_reg[25]} {axiSDC/response_0_reg[26]} {axiSDC/response_0_reg[27]} {axiSDC/response_0_reg[28]} {axiSDC/response_0_reg[29]} {axiSDC/response_0_reg[30]} {axiSDC/response_0_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe180] +set_property port_width 32 [get_debug_ports u_ila_0/probe180] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] -connect_debug_port u_ila_0/probe180 [get_nets [list {BUS_axi_awprot[0]} {BUS_axi_awprot[1]} {BUS_axi_awprot[2]} ]] - +connect_debug_port u_ila_0/probe180 [get_nets [list {axiSDC/response_1_reg[0]} {axiSDC/response_1_reg[1]} {axiSDC/response_1_reg[2]} {axiSDC/response_1_reg[3]} {axiSDC/response_1_reg[4]} {axiSDC/response_1_reg[5]} {axiSDC/response_1_reg[6]} {axiSDC/response_1_reg[7]} {axiSDC/response_1_reg[8]} {axiSDC/response_1_reg[9]} {axiSDC/response_1_reg[10]} {axiSDC/response_1_reg[11]} {axiSDC/response_1_reg[12]} {axiSDC/response_1_reg[13]} {axiSDC/response_1_reg[14]} {axiSDC/response_1_reg[15]} {axiSDC/response_1_reg[16]} {axiSDC/response_1_reg[17]} {axiSDC/response_1_reg[18]} {axiSDC/response_1_reg[19]} {axiSDC/response_1_reg[20]} {axiSDC/response_1_reg[21]} {axiSDC/response_1_reg[22]} {axiSDC/response_1_reg[23]} {axiSDC/response_1_reg[24]} {axiSDC/response_1_reg[25]} {axiSDC/response_1_reg[26]} {axiSDC/response_1_reg[27]} {axiSDC/response_1_reg[28]} {axiSDC/response_1_reg[29]} {axiSDC/response_1_reg[30]} {axiSDC/response_1_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe181] +set_property port_width 32 [get_debug_ports u_ila_0/probe181] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] -connect_debug_port u_ila_0/probe181 [get_nets [list {BUS_axi_awvalid}]] - +connect_debug_port u_ila_0/probe181 [get_nets [list {axiSDC/response_2_reg[0]} {axiSDC/response_2_reg[1]} {axiSDC/response_2_reg[2]} {axiSDC/response_2_reg[3]} {axiSDC/response_2_reg[4]} {axiSDC/response_2_reg[5]} {axiSDC/response_2_reg[6]} {axiSDC/response_2_reg[7]} {axiSDC/response_2_reg[8]} {axiSDC/response_2_reg[9]} {axiSDC/response_2_reg[10]} {axiSDC/response_2_reg[11]} {axiSDC/response_2_reg[12]} {axiSDC/response_2_reg[13]} {axiSDC/response_2_reg[14]} {axiSDC/response_2_reg[15]} {axiSDC/response_2_reg[16]} {axiSDC/response_2_reg[17]} {axiSDC/response_2_reg[18]} {axiSDC/response_2_reg[19]} {axiSDC/response_2_reg[20]} {axiSDC/response_2_reg[21]} {axiSDC/response_2_reg[22]} {axiSDC/response_2_reg[23]} {axiSDC/response_2_reg[24]} {axiSDC/response_2_reg[25]} {axiSDC/response_2_reg[26]} {axiSDC/response_2_reg[27]} {axiSDC/response_2_reg[28]} {axiSDC/response_2_reg[29]} {axiSDC/response_2_reg[30]} {axiSDC/response_2_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe182] +set_property port_width 32 [get_debug_ports u_ila_0/probe182] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] -connect_debug_port u_ila_0/probe182 [get_nets [list {BUS_axi_awready}]] - +connect_debug_port u_ila_0/probe182 [get_nets [list {axiSDC/dma_addr_reg[0]} {axiSDC/dma_addr_reg[1]} {axiSDC/dma_addr_reg[2]} {axiSDC/dma_addr_reg[3]} {axiSDC/dma_addr_reg[4]} {axiSDC/dma_addr_reg[5]} {axiSDC/dma_addr_reg[6]} {axiSDC/dma_addr_reg[7]} {axiSDC/dma_addr_reg[8]} {axiSDC/dma_addr_reg[9]} {axiSDC/dma_addr_reg[10]} {axiSDC/dma_addr_reg[11]} {axiSDC/dma_addr_reg[12]} {axiSDC/dma_addr_reg[13]} {axiSDC/dma_addr_reg[14]} {axiSDC/dma_addr_reg[15]} {axiSDC/dma_addr_reg[16]} {axiSDC/dma_addr_reg[17]} {axiSDC/dma_addr_reg[18]} {axiSDC/dma_addr_reg[19]} {axiSDC/dma_addr_reg[20]} {axiSDC/dma_addr_reg[21]} {axiSDC/dma_addr_reg[22]} {axiSDC/dma_addr_reg[23]} {axiSDC/dma_addr_reg[24]} {axiSDC/dma_addr_reg[25]} {axiSDC/dma_addr_reg[26]} {axiSDC/dma_addr_reg[27]} {axiSDC/dma_addr_reg[28]} {axiSDC/dma_addr_reg[29]} {axiSDC/dma_addr_reg[30]} {axiSDC/dma_addr_reg[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe183] +set_property port_width 12 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] -connect_debug_port u_ila_0/probe183 [get_nets [list {BUS_axi_awlock}]] - +connect_debug_port u_ila_0/probe183 [get_nets [list {axiSDC/block_size_reg[0]} {axiSDC/block_size_reg[1]} {axiSDC/block_size_reg[2]} {axiSDC/block_size_reg[3]} {axiSDC/block_size_reg[4]} {axiSDC/block_size_reg[5]} {axiSDC/block_size_reg[6]} {axiSDC/block_size_reg[7]} {axiSDC/block_size_reg[8]} {axiSDC/block_size_reg[9]} {axiSDC/block_size_reg[10]} {axiSDC/block_size_reg[11]} ]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe184] +set_property port_width 2 [get_debug_ports u_ila_0/probe184] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {BUS_axi_wdata[0]} {BUS_axi_wdata[1]} {BUS_axi_wdata[2]} {BUS_axi_wdata[3]} {BUS_axi_wdata[4]} {BUS_axi_wdata[5]} {BUS_axi_wdata[6]} {BUS_axi_wdata[7]} {BUS_axi_wdata[8]} {BUS_axi_wdata[9]} {BUS_axi_wdata[10]} {BUS_axi_wdata[11]} {BUS_axi_wdata[12]} {BUS_axi_wdata[13]} {BUS_axi_wdata[14]} {BUS_axi_wdata[15]} {BUS_axi_wdata[16]} {BUS_axi_wdata[17]} {BUS_axi_wdata[18]} {BUS_axi_wdata[19]} {BUS_axi_wdata[20]} {BUS_axi_wdata[21]} {BUS_axi_wdata[22]} {BUS_axi_wdata[23]} {BUS_axi_wdata[24]} {BUS_axi_wdata[25]} {BUS_axi_wdata[26]} {BUS_axi_wdata[27]} {BUS_axi_wdata[28]} {BUS_axi_wdata[29]} {BUS_axi_wdata[30]} {BUS_axi_wdata[31]} {BUS_axi_wdata[32]} {BUS_axi_wdata[33]} {BUS_axi_wdata[34]} {BUS_axi_wdata[35]} {BUS_axi_wdata[36]} {BUS_axi_wdata[37]} {BUS_axi_wdata[38]} {BUS_axi_wdata[39]} {BUS_axi_wdata[40]} {BUS_axi_wdata[41]} {BUS_axi_wdata[42]} {BUS_axi_wdata[43]} {BUS_axi_wdata[44]} {BUS_axi_wdata[45]} {BUS_axi_wdata[46]} {BUS_axi_wdata[47]} {BUS_axi_wdata[48]} {BUS_axi_wdata[49]} {BUS_axi_wdata[50]} {BUS_axi_wdata[51]} {BUS_axi_wdata[52]} {BUS_axi_wdata[53]} {BUS_axi_wdata[54]} {BUS_axi_wdata[55]} {BUS_axi_wdata[56]} {BUS_axi_wdata[57]} {BUS_axi_wdata[58]} {BUS_axi_wdata[59]} {BUS_axi_wdata[60]} {BUS_axi_wdata[61]} {BUS_axi_wdata[62]} {BUS_axi_wdata[63]} ]] - +connect_debug_port u_ila_0/probe184 [get_nets [list {axiSDC/controller_setting_reg[0]} {axiSDC/controller_setting_reg[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe185] +set_property port_width 5 [get_debug_ports u_ila_0/probe185] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185] -connect_debug_port u_ila_0/probe185 [get_nets [list {BUS_axi_wstrb[0]} {BUS_axi_wstrb[1]} {BUS_axi_wstrb[2]} {BUS_axi_wstrb[3]} {BUS_axi_wstrb[4]} {BUS_axi_wstrb[5]} {BUS_axi_wstrb[6]} {BUS_axi_wstrb[7]} ]] - +connect_debug_port u_ila_0/probe185 [get_nets [list {axiSDC/cmd_int_status_reg[0]} {axiSDC/cmd_int_status_reg[1]} {axiSDC/cmd_int_status_reg[2]} {axiSDC/cmd_int_status_reg[3]} {axiSDC/cmd_int_status_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe186] +set_property port_width 6 [get_debug_ports u_ila_0/probe186] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186] -connect_debug_port u_ila_0/probe186 [get_nets [list {BUS_axi_wlast}]] - +connect_debug_port u_ila_0/probe186 [get_nets [list {axiSDC/data_int_status_reg[0]} {axiSDC/data_int_status_reg[1]} {axiSDC/data_int_status_reg[2]} {axiSDC/data_int_status_reg[3]} {axiSDC/data_int_status_reg[4]} {axiSDC/data_int_status_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe187] +set_property port_width 6 [get_debug_ports u_ila_0/probe187] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187] -connect_debug_port u_ila_0/probe187 [get_nets [list {BUS_axi_wvalid}]] - +connect_debug_port u_ila_0/probe187 [get_nets [list {axiSDC/data_int_status[0]} {axiSDC/data_int_status[1]} {axiSDC/data_int_status[2]} {axiSDC/data_int_status[3]} {axiSDC/data_int_status[4]} {axiSDC/data_int_status[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe188] +set_property port_width 5 [get_debug_ports u_ila_0/probe188] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188] -connect_debug_port u_ila_0/probe188 [get_nets [list {BUS_axi_wready}]] - +connect_debug_port u_ila_0/probe188 [get_nets [list {axiSDC/cmd_int_enable_reg[0]} {axiSDC/cmd_int_enable_reg[1]} {axiSDC/cmd_int_enable_reg[2]} {axiSDC/cmd_int_enable_reg[3]} {axiSDC/cmd_int_enable_reg[4]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe189] +set_property port_width 6 [get_debug_ports u_ila_0/probe189] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189] -connect_debug_port u_ila_0/probe189 [get_nets [list {BUS_axi_bid[0]} {BUS_axi_bid[1]} {BUS_axi_bid[2]} {BUS_axi_bid[3]} ]] - +connect_debug_port u_ila_0/probe189 [get_nets [list {axiSDC/data_int_enable_reg[0]} {axiSDC/data_int_enable_reg[1]} {axiSDC/data_int_enable_reg[2]} {axiSDC/data_int_enable_reg[3]} {axiSDC/data_int_enable_reg[4]} {axiSDC/data_int_enable_reg[5]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe190] +set_property port_width 16 [get_debug_ports u_ila_0/probe190] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190] -connect_debug_port u_ila_0/probe190 [get_nets [list {BUS_axi_bresp[0]} {BUS_axi_bresp[1]} ]] - +connect_debug_port u_ila_0/probe190 [get_nets [list {axiSDC/block_count_reg[0]} {axiSDC/block_count_reg[1]} {axiSDC/block_count_reg[2]} {axiSDC/block_count_reg[3]} {axiSDC/block_count_reg[4]} {axiSDC/block_count_reg[5]} {axiSDC/block_count_reg[6]} {axiSDC/block_count_reg[7]} {axiSDC/block_count_reg[8]} {axiSDC/block_count_reg[9]} {axiSDC/block_count_reg[10]} {axiSDC/block_count_reg[11]} {axiSDC/block_count_reg[12]} {axiSDC/block_count_reg[13]} {axiSDC/block_count_reg[14]} {axiSDC/block_count_reg[15]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe191] +set_property port_width 8 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] -connect_debug_port u_ila_0/probe191 [get_nets [list {BUS_axi_bvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe192] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] -connect_debug_port u_ila_0/probe192 [get_nets [list {BUS_axi_bready}]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe193] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] -connect_debug_port u_ila_0/probe193 [get_nets [list {BUS_axi_arid[0]} {BUS_axi_arid[1]} {BUS_axi_arid[2]} {BUS_axi_arid[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe194] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] -connect_debug_port u_ila_0/probe194 [get_nets [list {BUS_axi_arlen[0]} {BUS_axi_arlen[1]} {BUS_axi_arlen[2]} {BUS_axi_arlen[3]} {BUS_axi_arlen[4]} {BUS_axi_arlen[5]} {BUS_axi_arlen[6]} {BUS_axi_arlen[7]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe195] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] -connect_debug_port u_ila_0/probe195 [get_nets [list {BUS_axi_arsize[0]} {BUS_axi_arsize[1]} {BUS_axi_arsize[2]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe196] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] -connect_debug_port u_ila_0/probe196 [get_nets [list {BUS_axi_arburst[0]} {BUS_axi_arburst[1]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe197] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] -connect_debug_port u_ila_0/probe197 [get_nets [list {BUS_axi_arprot[0]} {BUS_axi_arprot[1]} {BUS_axi_arprot[2]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe198] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] -connect_debug_port u_ila_0/probe198 [get_nets [list {BUS_axi_arcache[0]} {BUS_axi_arcache[1]} {BUS_axi_arcache[2]} {BUS_axi_arcache[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe199] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] -connect_debug_port u_ila_0/probe199 [get_nets [list {BUS_axi_arvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe200] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] -connect_debug_port u_ila_0/probe200 [get_nets [list {BUS_axi_araddr[0]} {BUS_axi_araddr[1]} {BUS_axi_araddr[2]} {BUS_axi_araddr[3]} {BUS_axi_araddr[4]} {BUS_axi_araddr[5]} {BUS_axi_araddr[6]} {BUS_axi_araddr[7]} {BUS_axi_araddr[8]} {BUS_axi_araddr[9]} {BUS_axi_araddr[10]} {BUS_axi_araddr[11]} {BUS_axi_araddr[12]} {BUS_axi_araddr[13]} {BUS_axi_araddr[14]} {BUS_axi_araddr[15]} {BUS_axi_araddr[16]} {BUS_axi_araddr[17]} {BUS_axi_araddr[18]} {BUS_axi_araddr[19]} {BUS_axi_araddr[20]} {BUS_axi_araddr[21]} {BUS_axi_araddr[22]} {BUS_axi_araddr[23]} {BUS_axi_araddr[24]} {BUS_axi_araddr[25]} {BUS_axi_araddr[26]} {BUS_axi_araddr[27]} {BUS_axi_araddr[28]} {BUS_axi_araddr[29]} {BUS_axi_araddr[30]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe201] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] -connect_debug_port u_ila_0/probe201 [get_nets [list {BUS_axi_arlock}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe202] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] -connect_debug_port u_ila_0/probe202 [get_nets [list {BUS_axi_arready}]] - - -create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe203] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] -connect_debug_port u_ila_0/probe203 [get_nets [list {BUS_axi_rid[0]} {BUS_axi_rid[1]} {BUS_axi_rid[2]} {BUS_axi_rid[3]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe204] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] -connect_debug_port u_ila_0/probe204 [get_nets [list {BUS_axi_rdata[0]} {BUS_axi_rdata[1]} {BUS_axi_rdata[2]} {BUS_axi_rdata[3]} {BUS_axi_rdata[4]} {BUS_axi_rdata[5]} {BUS_axi_rdata[6]} {BUS_axi_rdata[7]} {BUS_axi_rdata[8]} {BUS_axi_rdata[9]} {BUS_axi_rdata[10]} {BUS_axi_rdata[11]} {BUS_axi_rdata[12]} {BUS_axi_rdata[13]} {BUS_axi_rdata[14]} {BUS_axi_rdata[15]} {BUS_axi_rdata[16]} {BUS_axi_rdata[17]} {BUS_axi_rdata[18]} {BUS_axi_rdata[19]} {BUS_axi_rdata[20]} {BUS_axi_rdata[21]} {BUS_axi_rdata[22]} {BUS_axi_rdata[23]} {BUS_axi_rdata[24]} {BUS_axi_rdata[25]} {BUS_axi_rdata[26]} {BUS_axi_rdata[27]} {BUS_axi_rdata[28]} {BUS_axi_rdata[29]} {BUS_axi_rdata[30]} {BUS_axi_rdata[31]} {BUS_axi_rdata[32]} {BUS_axi_rdata[33]} {BUS_axi_rdata[34]} {BUS_axi_rdata[35]} {BUS_axi_rdata[36]} {BUS_axi_rdata[37]} {BUS_axi_rdata[38]} {BUS_axi_rdata[39]} {BUS_axi_rdata[40]} {BUS_axi_rdata[41]} {BUS_axi_rdata[42]} {BUS_axi_rdata[43]} {BUS_axi_rdata[44]} {BUS_axi_rdata[45]} {BUS_axi_rdata[46]} {BUS_axi_rdata[47]} {BUS_axi_rdata[48]} {BUS_axi_rdata[49]} {BUS_axi_rdata[50]} {BUS_axi_rdata[51]} {BUS_axi_rdata[52]} {BUS_axi_rdata[53]} {BUS_axi_rdata[54]} {BUS_axi_rdata[55]} {BUS_axi_rdata[56]} {BUS_axi_rdata[57]} {BUS_axi_rdata[58]} {BUS_axi_rdata[59]} {BUS_axi_rdata[60]} {BUS_axi_rdata[61]} {BUS_axi_rdata[62]} {BUS_axi_rdata[63]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe205] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] -connect_debug_port u_ila_0/probe205 [get_nets [list {BUS_axi_rresp[0]} {BUS_axi_rresp[1]} ]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe206] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] -connect_debug_port u_ila_0/probe206 [get_nets [list {BUS_axi_rvalid}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe207] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] -connect_debug_port u_ila_0/probe207 [get_nets [list {BUS_axi_rlast}]] - - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe208] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] -connect_debug_port u_ila_0/probe208 [get_nets [list {BUS_axi_rready}]] +connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index e2eb8441e..03758249e 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -139,41 +139,41 @@ module fpgaTop wire [3:0] BUS_axi_awqos; // Bus signals - (* mark_debug = "true" *) wire [3:0] BUS_axi_awid; - (* mark_debug = "true" *) wire [7:0] BUS_axi_awlen; - (* mark_debug = "true" *) wire [2:0] BUS_axi_awsize; - (* mark_debug = "true" *) wire [1:0] BUS_axi_awburst; - (* mark_debug = "true" *) wire [3:0] BUS_axi_awcache; - (* mark_debug = "true" *) wire [30:0] BUS_axi_awaddr; - (* mark_debug = "true" *) wire [2:0] BUS_axi_awprot; - (* mark_debug = "true" *) wire BUS_axi_awvalid; - (* mark_debug = "true" *) wire BUS_axi_awready; - (* mark_debug = "true" *) wire BUS_axi_awlock; - (* mark_debug = "true" *) wire [63:0] BUS_axi_wdata; - (* mark_debug = "true" *) wire [7:0] BUS_axi_wstrb; - (* mark_debug = "true" *) wire BUS_axi_wlast; - (* mark_debug = "true" *) wire BUS_axi_wvalid; - (* mark_debug = "true" *) wire BUS_axi_wready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_bid; - (* mark_debug = "true" *) wire [1:0] BUS_axi_bresp; - (* mark_debug = "true" *) wire BUS_axi_bvalid; - (* mark_debug = "true" *) wire BUS_axi_bready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_arid; - (* mark_debug = "true" *) wire [7:0] BUS_axi_arlen; - (* mark_debug = "true" *) wire [2:0] BUS_axi_arsize; - (* mark_debug = "true" *) wire [1:0] BUS_axi_arburst; - (* mark_debug = "true" *) wire [2:0] BUS_axi_arprot; - (* mark_debug = "true" *) wire [3:0] BUS_axi_arcache; - (* mark_debug = "true" *) wire BUS_axi_arvalid; - (* mark_debug = "true" *) wire [30:0] BUS_axi_araddr; - (* mark_debug = "true" *) wire BUS_axi_arlock; - (* mark_debug = "true" *) wire BUS_axi_arready; - (* mark_debug = "true" *) wire [3:0] BUS_axi_rid; - (* mark_debug = "true" *) wire [63:0] BUS_axi_rdata; - (* mark_debug = "true" *) wire [1:0] BUS_axi_rresp; - (* mark_debug = "true" *) wire BUS_axi_rvalid; - (* mark_debug = "true" *) wire BUS_axi_rlast; - (* mark_debug = "true" *) wire BUS_axi_rready; + wire [3:0] BUS_axi_awid; + wire [7:0] BUS_axi_awlen; + wire [2:0] BUS_axi_awsize; + wire [1:0] BUS_axi_awburst; + wire [3:0] BUS_axi_awcache; + wire [30:0] BUS_axi_awaddr; + wire [2:0] BUS_axi_awprot; + wire BUS_axi_awvalid; + wire BUS_axi_awready; + wire BUS_axi_awlock; + wire [63:0] BUS_axi_wdata; + wire [7:0] BUS_axi_wstrb; + wire BUS_axi_wlast; + wire BUS_axi_wvalid; + wire BUS_axi_wready; + wire [3:0] BUS_axi_bid; + wire [1:0] BUS_axi_bresp; + wire BUS_axi_bvalid; + wire BUS_axi_bready; + wire [3:0] BUS_axi_arid; + wire [7:0] BUS_axi_arlen; + wire [2:0] BUS_axi_arsize; + wire [1:0] BUS_axi_arburst; + wire [2:0] BUS_axi_arprot; + wire [3:0] BUS_axi_arcache; + wire BUS_axi_arvalid; + wire [30:0] BUS_axi_araddr; + wire BUS_axi_arlock; + wire BUS_axi_arready; + wire [3:0] BUS_axi_rid; + wire [63:0] BUS_axi_rdata; + wire [1:0] BUS_axi_rresp; + wire BUS_axi_rvalid; + wire BUS_axi_rlast; + wire BUS_axi_rready; wire BUSCLK; @@ -225,6 +225,9 @@ module fpgaTop wire s00_axi_rlast; wire s00_axi_rvalid; wire s00_axi_rready; + + wire [3:0] s00_axi_bid; + wire [3:0] s00_axi_rid; // 64to32 dwidth converter input interface------------------------- wire s01_axi_aclk; @@ -508,7 +511,8 @@ module fpgaTop .SDCCmdOut(SDCCmdOut), .SDCCmdOE(SDCCmdOE), .SDCCLK(SDCCLK));*/ - + ); + // ahb lite to axi bridge xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 (.s_ahb_hclk(CPUCLK), @@ -567,7 +571,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({4'b0, m_axi_awid}), + .s_axi_awid({4'b0001, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -587,7 +591,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b0, m_axi_arid}), + .s_axi_arid({4'b0001, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -623,7 +627,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b0, s00_axi_bid}), + .m_axi_bid({4'b0001, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -878,7 +882,7 @@ module fpgaTop .s_axi_awvalid(SDCout_axi_awvalid), .s_axi_awready(SDCout_axi_awready), .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(4'b0), + .s_axi_wstrb(8'b0), .s_axi_wlast(SDCout_axi_wlast), .s_axi_wvalid(SDCout_axi_wvalid), .s_axi_wready(SDCout_axi_wready), diff --git a/pipelined/src/uncore/newsdc/axi_sdc_controller.v b/pipelined/src/uncore/newsdc/axi_sdc_controller.v index d900ddbbd..7e206c676 100644 --- a/pipelined/src/uncore/newsdc/axi_sdc_controller.v +++ b/pipelined/src/uncore/newsdc/axi_sdc_controller.v @@ -175,25 +175,25 @@ reg data_int_rst; reg ctrl_rst; // AXI accessible registers -reg [31:0] argument_reg; -reg [`CMD_REG_SIZE-1:0] command_reg; -reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg; -reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg; -reg [0:0] software_reset_reg; -wire [31:0] response_0_reg; -wire [31:0] response_1_reg; -wire [31:0] response_2_reg; -wire [31:0] response_3_reg; -reg [`BLKSIZE_W-1:0] block_size_reg; -reg [1:0] controller_setting_reg; -wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg; -wire [`INT_DATA_SIZE-1:0] data_int_status_reg; -wire [`INT_DATA_SIZE-1:0] data_int_status; -reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg; -reg [`INT_DATA_SIZE-1:0] data_int_enable_reg; -reg [`BLKCNT_W-1:0] block_count_reg; -reg [dma_addr_bits-1:0] dma_addr_reg; -reg [7:0] clock_divider_reg = 124; // 400KHz +(* mark_debug = "true" *) reg [31:0] argument_reg; +(* mark_debug = "true" *) reg [`CMD_REG_SIZE-1:0] command_reg; +(* mark_debug = "true" *) reg [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg; +(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] data_timeout_reg; +(* mark_debug = "true" *) reg [0:0] software_reset_reg; +(* mark_debug = "true" *) wire [31:0] response_0_reg; +(* mark_debug = "true" *) wire [31:0] response_1_reg; +(* mark_debug = "true" *) wire [31:0] response_2_reg; +(* mark_debug = "true" *) wire [31:0] response_3_reg; +(* mark_debug = "true" *) reg [`BLKSIZE_W-1:0] block_size_reg; +(* mark_debug = "true" *) reg [1:0] controller_setting_reg; +(* mark_debug = "true" *) wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg; +(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status_reg; +(* mark_debug = "true" *) wire [`INT_DATA_SIZE-1:0] data_int_status; +(* mark_debug = "true" *) reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg; +(* mark_debug = "true" *) reg [`INT_DATA_SIZE-1:0] data_int_enable_reg; +(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] block_count_reg; +(* mark_debug = "true" *) reg [dma_addr_bits-1:0] dma_addr_reg; +(* mark_debug = "true" *) reg [7:0] clock_divider_reg = 124; // 400KHz // ------ Clocks and resets @@ -206,7 +206,7 @@ always @(posedge clock) reg [7:0] clock_cnt; reg clock_state; -reg clock_posedge; +(* mark_debug = "true" *) reg clock_posedge; reg clock_data_in; wire fifo_almost_full; wire fifo_almost_empty; diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 64cb9224b..927462c78 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -52,7 +52,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, // for FPGA, initialize with zero-stage bootloader if(PRELOAD_ENABLED) begin initial begin - ROM[0] = 64'h9581819300002197; + /*ROM[0] = 64'h9581819300002197; ROM[1] = 64'h4281420141014081; ROM[2] = 64'h4481440143814301; ROM[3] = 64'h4681460145814501; @@ -94,7 +94,649 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ROM[39] = 64'h1047278367498082; ROM[40] = 64'h47858082dfed8b85; ROM[41] = 64'h40a7853b4015551b; - ROM[42] = 64'h808210a7a02367c9; + ROM[42] = 64'h808210a7a02367c9;*/ + + ROM[0] = 64'hc001819300002197; + ROM[1] = 64'h4281420141014081; + ROM[2] = 64'h4481440143814301; + ROM[3] = 64'h4681460145814501; + ROM[4] = 64'h4881480147814701; + ROM[5] = 64'h4a814a0149814901; + ROM[6] = 64'h4c814c014b814b01; + ROM[7] = 64'h4e814e014d814d01; + ROM[8] = 64'h0110011b4f814f01; + ROM[9] = 64'h059b45011161016e; + ROM[10] = 64'h0004063705fe0010; + ROM[11] = 64'h1ee000ef8006061b; + ROM[12] = 64'h0ff003930000100f; + ROM[13] = 64'h4e952e3110060e37; + ROM[14] = 64'hc602829b0053f2b7; + ROM[15] = 64'h2023fe02dfe312fd; + ROM[16] = 64'h829b0053f2b7007e; + ROM[17] = 64'hfe02dfe312fdc602; + ROM[18] = 64'h4de31efd000e2023; + ROM[19] = 64'h059bf1402573fdd0; + ROM[20] = 64'h0000061705e20870; + ROM[21] = 64'h0010029b01260613; + ROM[22] = 64'h67110002806702fe; + ROM[23] = 64'h0085179bf0070713; + ROM[24] = 64'h2781038007138ff9; + ROM[25] = 64'h7563470508a76a63; + ROM[26] = 64'h00a71733357902a7; + ROM[27] = 64'h3285350300001517; + ROM[28] = 64'h40301537e9598d79; + ROM[29] = 64'h8d7942250513051a; + ROM[30] = 64'he35d18177713e149; + ROM[31] = 64'he79300367713c295; + ROM[32] = 64'hf330674de3450207; + ROM[33] = 64'h861bc3701ff00613; + ROM[34] = 64'h01000637c730fff6; + ROM[35] = 64'hc35c674dcf10167d; + ROM[36] = 64'hd31c17fd001007b7; + ROM[37] = 64'h0007861b5b5cc30c; + ROM[38] = 64'h674d02072a23dfed; + ROM[39] = 64'h12634785fffd571c; + ROM[40] = 64'h80818793471006f6; + ROM[41] = 64'h4b10474cc3904501; + ROM[42] = 64'hc7d8c790c3cc4b58; + ROM[43] = 64'h086007138082e29d; + ROM[44] = 64'h0a90071300e50c63; + ROM[45] = 64'h0017e793f8e518e3; + ROM[46] = 64'hb74901d7e793b761; + ROM[47] = 64'h674dbfb50197e793; + ROM[48] = 64'h02072e23dffd5f5c; + ROM[49] = 64'h8513ff7d569866cd; + ROM[50] = 64'h053300a03533fff7; + ROM[51] = 64'h00a7e793808240a0; + ROM[52] = 64'h71398082557dbfa1; + ROM[53] = 64'hf8228181ca03e852; + ROM[54] = 64'hf426fc06ec4ef04a; + ROM[55] = 64'h008a7a13e05ae456; + ROM[56] = 64'h1463843289ae892a; + ROM[57] = 64'h4a8500959993000a; + ROM[58] = 64'h4549864ac4296b05; + ROM[59] = 64'h055402630009859b; + ROM[60] = 64'h008b73630004049b; + ROM[61] = 64'hecbff0ef86a66485; + ROM[62] = 64'h45814601468187aa; + ROM[63] = 64'h0207c8639c054531; + ROM[64] = 64'h0094979beb7ff0ef; + ROM[65] = 64'h0205406393811782; + ROM[66] = 64'h99ba020a1863873e; + ROM[67] = 64'ha8014501fc4d993e; + ROM[68] = 64'he93ff0ef45454685; + ROM[69] = 64'h70e24505fe055ae3; + ROM[70] = 64'h69e2790274a27442; + ROM[71] = 64'h61216b026aa26a42; + ROM[72] = 64'h9301020497138082; + ROM[73] = 64'hec26f0227179b7f9; + ROM[74] = 64'he44ef4064705e84a; + ROM[75] = 64'h842e84aad79867cd; + ROM[76] = 64'h8b85571c674d8932; + ROM[77] = 64'hd35c03600793dff5; + ROM[78] = 64'h571c674d02072423; + ROM[79] = 64'ha737b00026f3fffd; + ROM[80] = 64'h27f311f707130007; + ROM[81] = 64'hfef77de38f95b000; + ROM[82] = 64'h80018c235b1c674d; + ROM[83] = 64'he7934f5ccf9d8b89; + ROM[84] = 64'hb00026f3cf5c0027; + ROM[85] = 64'h0ff7071305f5e737; + ROM[86] = 64'h7de38f95b00027f3; + ROM[87] = 64'h9bf54f5c674dfef7; + ROM[88] = 64'h9737b00026f3cf5c; + ROM[89] = 64'h27f367f707130098; + ROM[90] = 64'hfef77de38f95b000; + ROM[91] = 64'h4501458146014681; + ROM[92] = 64'h80818993dd7ff0ef; + ROM[93] = 64'h0593460146814789; + ROM[94] = 64'h00f9882345211aa0; + ROM[95] = 64'ha783e50ddbfff0ef; + ROM[96] = 64'h17d21aa007130009; + ROM[97] = 64'h479102e79e6393d1; + ROM[98] = 64'hf0efa80900f98823; + ROM[99] = 64'ha78302054663da1f; + ROM[100]= 64'h46810207cc630009; + ROM[101]= 64'h0370051345814601; + ROM[102]= 64'h468187aad87ff0ef; + ROM[103]= 64'h0513403005b74601; + ROM[104]= 64'h8522fc07dae30a90; + ROM[105]= 64'h864a69a270a27402; + ROM[106]= 64'h614564e2694285a6; + ROM[107]= 64'hebd18b8583f9b5b9; + ROM[108]= 64'h4509458146014681; + ROM[109]= 64'hfc054de3d4fff0ef; + ROM[110]= 64'h123405b746014681; + ROM[111]= 64'h44e3d3dff0ef450d; + ROM[112]= 64'h77c10009a983fc05; + ROM[113]= 64'h460100f9f9b34681; + ROM[114]= 64'hd23ff0ef451d85ce; + ROM[115]= 64'h470567cdfa0547e3; + ROM[116]= 64'h4737b00026f3d3d8; + ROM[117]= 64'h27f323f70713000f; + ROM[118]= 64'hfef77de38f95b000; + ROM[119]= 64'h46810007ae2367cd; + ROM[120]= 64'h0370051385ce4601; + ROM[121]= 64'hf6054de3cefff0ef; + ROM[122]= 64'h0513458146014681; + ROM[123]= 64'h44e3cddff0ef0860; + ROM[124]= 64'h059346014681f605; + ROM[125]= 64'hccbff0ef45412000; + ROM[126]= 64'he7930109c783bf99; + ROM[127]= 64'hb78d00f988230087; + ROM[128]= 64'h0000000000000000; + ROM[129]= 64'h0000000000000000; + ROM[130]= 64'h0000000000000000; + ROM[131]= 64'h0000000000000000; + ROM[132]= 64'h0000000000000000; + ROM[133]= 64'h0000000000000000; + ROM[134]= 64'h0000000000000000; + ROM[135]= 64'h0000000000000000; + ROM[136]= 64'h0000000000000000; + ROM[137]= 64'h0000000000000000; + ROM[138]= 64'h0000000000000000; + ROM[139]= 64'h0000000000000000; + ROM[140]= 64'h0000000000000000; + ROM[141]= 64'h0000000000000000; + ROM[142]= 64'h0000000000000000; + ROM[143]= 64'h0000000000000000; + ROM[144]= 64'h0000000000000000; + ROM[145]= 64'h0000000000000000; + ROM[146]= 64'h0000000000000000; + ROM[147]= 64'h0000000000000000; + ROM[148]= 64'h0000000000000000; + ROM[149]= 64'h0000000000000000; + ROM[150]= 64'h0000000000000000; + ROM[151]= 64'h0000000000000000; + ROM[152]= 64'h0000000000000000; + ROM[153]= 64'h0000000000000000; + ROM[154]= 64'h0000000000000000; + ROM[155]= 64'h0000000000000000; + ROM[156]= 64'h0000000000000000; + ROM[157]= 64'h0000000000000000; + ROM[158]= 64'h0000000000000000; + ROM[159]= 64'h0000000000000000; + ROM[160]= 64'h0000000000000000; + ROM[161]= 64'h0000000000000000; + ROM[162]= 64'h0000000000000000; + ROM[163]= 64'h0000000000000000; + ROM[164]= 64'h0000000000000000; + ROM[165]= 64'h0000000000000000; + ROM[166]= 64'h0000000000000000; + ROM[167]= 64'h0000000000000000; + ROM[168]= 64'h0000000000000000; + ROM[169]= 64'h0000000000000000; + ROM[170]= 64'h0000000000000000; + ROM[171]= 64'h0000000000000000; + ROM[172]= 64'h0000000000000000; + ROM[173]= 64'h0000000000000000; + ROM[174]= 64'h0000000000000000; + ROM[175]= 64'h0000000000000000; + ROM[176]= 64'h0000000000000000; + ROM[177]= 64'h0000000000000000; + ROM[178]= 64'h0000000000000000; + ROM[179]= 64'h0000000000000000; + ROM[180]= 64'h0000000000000000; + ROM[181]= 64'h0000000000000000; + ROM[182]= 64'h0000000000000000; + ROM[183]= 64'h0000000000000000; + ROM[184]= 64'h0000000000000000; + ROM[185]= 64'h0000000000000000; + ROM[186]= 64'h0000000000000000; + ROM[187]= 64'h0000000000000000; + ROM[188]= 64'h0000000000000000; + ROM[189]= 64'h0000000000000000; + ROM[190]= 64'h0000000000000000; + ROM[191]= 64'h0000000000000000; + ROM[192]= 64'h0000000000000000; + ROM[193]= 64'h0000000000000000; + ROM[194]= 64'h0000000000000000; + ROM[195]= 64'h0000000000000000; + ROM[196]= 64'h0000000000000000; + ROM[197]= 64'h0000000000000000; + ROM[198]= 64'h0000000000000000; + ROM[199]= 64'h0000000000000000; + ROM[200]= 64'h0000000000000000; + ROM[201]= 64'h0000000000000000; + ROM[202]= 64'h0000000000000000; + ROM[203]= 64'h0000000000000000; + ROM[204]= 64'h0000000000000000; + ROM[205]= 64'h0000000000000000; + ROM[206]= 64'h0000000000000000; + ROM[207]= 64'h0000000000000000; + ROM[208]= 64'h0000000000000000; + ROM[209]= 64'h0000000000000000; + ROM[210]= 64'h0000000000000000; + ROM[211]= 64'h0000000000000000; + ROM[212]= 64'h0000000000000000; + ROM[213]= 64'h0000000000000000; + ROM[214]= 64'h0000000000000000; + ROM[215]= 64'h0000000000000000; + ROM[216]= 64'h0000000000000000; + ROM[217]= 64'h0000000000000000; + ROM[218]= 64'h0000000000000000; + ROM[219]= 64'h0000000000000000; + ROM[220]= 64'h0000000000000000; + ROM[221]= 64'h0000000000000000; + ROM[222]= 64'h0000000000000000; + ROM[223]= 64'h0000000000000000; + ROM[224]= 64'h0000000000000000; + ROM[225]= 64'h0000000000000000; + ROM[226]= 64'h0000000000000000; + ROM[227]= 64'h0000000000000000; + ROM[228]= 64'h0000000000000000; + ROM[229]= 64'h0000000000000000; + ROM[230]= 64'h0000000000000000; + ROM[231]= 64'h0000000000000000; + ROM[232]= 64'h0000000000000000; + ROM[233]= 64'h0000000000000000; + ROM[234]= 64'h0000000000000000; + ROM[235]= 64'h0000000000000000; + ROM[236]= 64'h0000000000000000; + ROM[237]= 64'h0000000000000000; + ROM[238]= 64'h0000000000000000; + ROM[239]= 64'h0000000000000000; + ROM[240]= 64'h0000000000000000; + ROM[241]= 64'h0000000000000000; + ROM[242]= 64'h0000000000000000; + ROM[243]= 64'h0000000000000000; + ROM[244]= 64'h0000000000000000; + ROM[245]= 64'h0000000000000000; + ROM[246]= 64'h0000000000000000; + ROM[247]= 64'h0000000000000000; + ROM[248]= 64'h0000000000000000; + ROM[249]= 64'h0000000000000000; + ROM[250]= 64'h0000000000000000; + ROM[251]= 64'h0000000000000000; + ROM[252]= 64'h0000000000000000; + ROM[253]= 64'h0000000000000000; + ROM[254]= 64'h0000000000000000; + ROM[255]= 64'h0000000000000000; + ROM[256]= 64'h0000000000000000; + ROM[257]= 64'h0000000000000000; + ROM[258]= 64'h0000000000000000; + ROM[259]= 64'h0000000000000000; + ROM[260]= 64'h0000000000000000; + ROM[261]= 64'h0000000000000000; + ROM[262]= 64'h0000000000000000; + ROM[263]= 64'h0000000000000000; + ROM[264]= 64'h0000000000000000; + ROM[265]= 64'h0000000000000000; + ROM[266]= 64'h0000000000000000; + ROM[267]= 64'h0000000000000000; + ROM[268]= 64'h0000000000000000; + ROM[269]= 64'h0000000000000000; + ROM[270]= 64'h0000000000000000; + ROM[271]= 64'h0000000000000000; + ROM[272]= 64'h0000000000000000; + ROM[273]= 64'h0000000000000000; + ROM[274]= 64'h0000000000000000; + ROM[275]= 64'h0000000000000000; + ROM[276]= 64'h0000000000000000; + ROM[277]= 64'h0000000000000000; + ROM[278]= 64'h0000000000000000; + ROM[279]= 64'h0000000000000000; + ROM[280]= 64'h0000000000000000; + ROM[281]= 64'h0000000000000000; + ROM[282]= 64'h0000000000000000; + ROM[283]= 64'h0000000000000000; + ROM[284]= 64'h0000000000000000; + ROM[285]= 64'h0000000000000000; + ROM[286]= 64'h0000000000000000; + ROM[287]= 64'h0000000000000000; + ROM[288]= 64'h0000000000000000; + ROM[289]= 64'h0000000000000000; + ROM[290]= 64'h0000000000000000; + ROM[291]= 64'h0000000000000000; + ROM[292]= 64'h0000000000000000; + ROM[293]= 64'h0000000000000000; + ROM[294]= 64'h0000000000000000; + ROM[295]= 64'h0000000000000000; + ROM[296]= 64'h0000000000000000; + ROM[297]= 64'h0000000000000000; + ROM[298]= 64'h0000000000000000; + ROM[299]= 64'h0000000000000000; + ROM[300]= 64'h0000000000000000; + ROM[301]= 64'h0000000000000000; + ROM[302]= 64'h0000000000000000; + ROM[303]= 64'h0000000000000000; + ROM[304]= 64'h0000000000000000; + ROM[305]= 64'h0000000000000000; + ROM[306]= 64'h0000000000000000; + ROM[307]= 64'h0000000000000000; + ROM[308]= 64'h0000000000000000; + ROM[309]= 64'h0000000000000000; + ROM[310]= 64'h0000000000000000; + ROM[311]= 64'h0000000000000000; + ROM[312]= 64'h0000000000000000; + ROM[313]= 64'h0000000000000000; + ROM[314]= 64'h0000000000000000; + ROM[315]= 64'h0000000000000000; + ROM[316]= 64'h0000000000000000; + ROM[317]= 64'h0000000000000000; + ROM[318]= 64'h0000000000000000; + ROM[319]= 64'h0000000000000000; + ROM[320]= 64'h0000000000000000; + ROM[321]= 64'h0000000000000000; + ROM[322]= 64'h0000000000000000; + ROM[323]= 64'h0000000000000000; + ROM[324]= 64'h0000000000000000; + ROM[325]= 64'h0000000000000000; + ROM[326]= 64'h0000000000000000; + ROM[327]= 64'h0000000000000000; + ROM[328]= 64'h0000000000000000; + ROM[329]= 64'h0000000000000000; + ROM[330]= 64'h0000000000000000; + ROM[331]= 64'h0000000000000000; + ROM[332]= 64'h0000000000000000; + ROM[333]= 64'h0000000000000000; + ROM[334]= 64'h0000000000000000; + ROM[335]= 64'h0000000000000000; + ROM[336]= 64'h0000000000000000; + ROM[337]= 64'h0000000000000000; + ROM[338]= 64'h0000000000000000; + ROM[339]= 64'h0000000000000000; + ROM[340]= 64'h0000000000000000; + ROM[341]= 64'h0000000000000000; + ROM[342]= 64'h0000000000000000; + ROM[343]= 64'h0000000000000000; + ROM[344]= 64'h0000000000000000; + ROM[345]= 64'h0000000000000000; + ROM[346]= 64'h0000000000000000; + ROM[347]= 64'h0000000000000000; + ROM[348]= 64'h0000000000000000; + ROM[349]= 64'h0000000000000000; + ROM[350]= 64'h0000000000000000; + ROM[351]= 64'h0000000000000000; + ROM[352]= 64'h0000000000000000; + ROM[353]= 64'h0000000000000000; + ROM[354]= 64'h0000000000000000; + ROM[355]= 64'h0000000000000000; + ROM[356]= 64'h0000000000000000; + ROM[357]= 64'h0000000000000000; + ROM[358]= 64'h0000000000000000; + ROM[359]= 64'h0000000000000000; + ROM[360]= 64'h0000000000000000; + ROM[361]= 64'h0000000000000000; + ROM[362]= 64'h0000000000000000; + ROM[363]= 64'h0000000000000000; + ROM[364]= 64'h0000000000000000; + ROM[365]= 64'h0000000000000000; + ROM[366]= 64'h0000000000000000; + ROM[367]= 64'h0000000000000000; + ROM[368]= 64'h0000000000000000; + ROM[369]= 64'h0000000000000000; + ROM[370]= 64'h0000000000000000; + ROM[371]= 64'h0000000000000000; + ROM[372]= 64'h0000000000000000; + ROM[373]= 64'h0000000000000000; + ROM[374]= 64'h0000000000000000; + ROM[375]= 64'h0000000000000000; + ROM[376]= 64'h0000000000000000; + ROM[377]= 64'h0000000000000000; + ROM[378]= 64'h0000000000000000; + ROM[379]= 64'h0000000000000000; + ROM[380]= 64'h0000000000000000; + ROM[381]= 64'h0000000000000000; + ROM[382]= 64'h0000000000000000; + ROM[383]= 64'h0000000000000000; + ROM[384]= 64'h0000000000000000; + ROM[385]= 64'h0000000000000000; + ROM[386]= 64'h0000000000000000; + ROM[387]= 64'h0000000000000000; + ROM[388]= 64'h0000000000000000; + ROM[389]= 64'h0000000000000000; + ROM[390]= 64'h0000000000000000; + ROM[391]= 64'h0000000000000000; + ROM[392]= 64'h0000000000000000; + ROM[393]= 64'h0000000000000000; + ROM[394]= 64'h0000000000000000; + ROM[395]= 64'h0000000000000000; + ROM[396]= 64'h0000000000000000; + ROM[397]= 64'h0000000000000000; + ROM[398]= 64'h0000000000000000; + ROM[399]= 64'h0000000000000000; + ROM[400]= 64'h0000000000000000; + ROM[401]= 64'h0000000000000000; + ROM[402]= 64'h0000000000000000; + ROM[403]= 64'h0000000000000000; + ROM[404]= 64'h0000000000000000; + ROM[405]= 64'h0000000000000000; + ROM[406]= 64'h0000000000000000; + ROM[407]= 64'h0000000000000000; + ROM[408]= 64'h0000000000000000; + ROM[409]= 64'h0000000000000000; + ROM[410]= 64'h0000000000000000; + ROM[411]= 64'h0000000000000000; + ROM[412]= 64'h0000000000000000; + ROM[413]= 64'h0000000000000000; + ROM[414]= 64'h0000000000000000; + ROM[415]= 64'h0000000000000000; + ROM[416]= 64'h0000000000000000; + ROM[417]= 64'h0000000000000000; + ROM[418]= 64'h0000000000000000; + ROM[419]= 64'h0000000000000000; + ROM[420]= 64'h0000000000000000; + ROM[421]= 64'h0000000000000000; + ROM[422]= 64'h0000000000000000; + ROM[423]= 64'h0000000000000000; + ROM[424]= 64'h0000000000000000; + ROM[425]= 64'h0000000000000000; + ROM[426]= 64'h0000000000000000; + ROM[427]= 64'h0000000000000000; + ROM[428]= 64'h0000000000000000; + ROM[429]= 64'h0000000000000000; + ROM[430]= 64'h0000000000000000; + ROM[431]= 64'h0000000000000000; + ROM[432]= 64'h0000000000000000; + ROM[433]= 64'h0000000000000000; + ROM[434]= 64'h0000000000000000; + ROM[435]= 64'h0000000000000000; + ROM[436]= 64'h0000000000000000; + ROM[437]= 64'h0000000000000000; + ROM[438]= 64'h0000000000000000; + ROM[439]= 64'h0000000000000000; + ROM[440]= 64'h0000000000000000; + ROM[441]= 64'h0000000000000000; + ROM[442]= 64'h0000000000000000; + ROM[443]= 64'h0000000000000000; + ROM[444]= 64'h0000000000000000; + ROM[445]= 64'h0000000000000000; + ROM[446]= 64'h0000000000000000; + ROM[447]= 64'h0000000000000000; + ROM[448]= 64'h0000000000000000; + ROM[449]= 64'h0000000000000000; + ROM[450]= 64'h0000000000000000; + ROM[451]= 64'h0000000000000000; + ROM[452]= 64'h0000000000000000; + ROM[453]= 64'h0000000000000000; + ROM[454]= 64'h0000000000000000; + ROM[455]= 64'h0000000000000000; + ROM[456]= 64'h0000000000000000; + ROM[457]= 64'h0000000000000000; + ROM[458]= 64'h0000000000000000; + ROM[459]= 64'h0000000000000000; + ROM[460]= 64'h0000000000000000; + ROM[461]= 64'h0000000000000000; + ROM[462]= 64'h0000000000000000; + ROM[463]= 64'h0000000000000000; + ROM[464]= 64'h0000000000000000; + ROM[465]= 64'h0000000000000000; + ROM[466]= 64'h0000000000000000; + ROM[467]= 64'h0000000000000000; + ROM[468]= 64'h0000000000000000; + ROM[469]= 64'h0000000000000000; + ROM[470]= 64'h0000000000000000; + ROM[471]= 64'h0000000000000000; + ROM[472]= 64'h0000000000000000; + ROM[473]= 64'h0000000000000000; + ROM[474]= 64'h0000000000000000; + ROM[475]= 64'h0000000000000000; + ROM[476]= 64'h0000000000000000; + ROM[477]= 64'h0000000000000000; + ROM[478]= 64'h0000000000000000; + ROM[479]= 64'h0000000000000000; + ROM[480]= 64'h0000000000000000; + ROM[481]= 64'h0000000000000000; + ROM[482]= 64'h0000000000000000; + ROM[483]= 64'h0000000000000000; + ROM[484]= 64'h0000000000000000; + ROM[485]= 64'h0000000000000000; + ROM[486]= 64'h0000000000000000; + ROM[487]= 64'h0000000000000000; + ROM[488]= 64'h0000000000000000; + ROM[489]= 64'h0000000000000000; + ROM[490]= 64'h0000000000000000; + ROM[491]= 64'h0000000000000000; + ROM[492]= 64'h0000000000000000; + ROM[493]= 64'h0000000000000000; + ROM[494]= 64'h0000000000000000; + ROM[495]= 64'h0000000000000000; + ROM[496]= 64'h0000000000000000; + ROM[497]= 64'h0000000000000000; + ROM[498]= 64'h0000000000000000; + ROM[499]= 64'h0000000000000000; + ROM[500]= 64'h0000000000000000; + ROM[501]= 64'h0000000000000000; + ROM[502]= 64'h0000000000000000; + ROM[503]= 64'h0000000000000000; + ROM[504]= 64'h0000000000000000; + ROM[505]= 64'h0000000000000000; + ROM[506]= 64'h0000000000000000; + ROM[507]= 64'h0000000000000000; + ROM[508]= 64'h0000000000000000; + ROM[509]= 64'h0000000000000000; + ROM[510]= 64'h0000000000000000; + ROM[511]= 64'h0000000000000000; + ROM[512]= 64'h0000000000000000; + ROM[513]= 64'h0000000000000000; + ROM[514]= 64'h0000000000000000; + ROM[515]= 64'h0000000000000000; + ROM[516]= 64'h0000000000000000; + ROM[517]= 64'h0000000000000000; + ROM[518]= 64'h0000000000000000; + ROM[519]= 64'h0000000000000000; + ROM[520]= 64'h0000000000000000; + ROM[521]= 64'h0000000000000000; + ROM[522]= 64'h0000000000000000; + ROM[523]= 64'h0000000000000000; + ROM[524]= 64'h0000000000000000; + ROM[525]= 64'h0000000000000000; + ROM[526]= 64'h0000000000000000; + ROM[527]= 64'h0000000000000000; + ROM[528]= 64'h0000000000000000; + ROM[529]= 64'h0000000000000000; + ROM[530]= 64'h0000000000000000; + ROM[531]= 64'h0000000000000000; + ROM[532]= 64'h0000000000000000; + ROM[533]= 64'h0000000000000000; + ROM[534]= 64'h0000000000000000; + ROM[535]= 64'h0000000000000000; + ROM[536]= 64'h0000000000000000; + ROM[537]= 64'h0000000000000000; + ROM[538]= 64'h0000000000000000; + ROM[539]= 64'h0000000000000000; + ROM[540]= 64'h0000000000000000; + ROM[541]= 64'h0000000000000000; + ROM[542]= 64'h0000000000000000; + ROM[543]= 64'h0000000000000000; + ROM[544]= 64'h0000000000000000; + ROM[545]= 64'h0000000000000000; + ROM[546]= 64'h0000000000000000; + ROM[547]= 64'h0000000000000000; + ROM[548]= 64'h0000000000000000; + ROM[549]= 64'h0000000000000000; + ROM[550]= 64'h0000000000000000; + ROM[551]= 64'h0000000000000000; + ROM[552]= 64'h0000000000000000; + ROM[553]= 64'h0000000000000000; + ROM[554]= 64'h0000000000000000; + ROM[555]= 64'h0000000000000000; + ROM[556]= 64'h0000000000000000; + ROM[557]= 64'h0000000000000000; + ROM[558]= 64'h0000000000000000; + ROM[559]= 64'h0000000000000000; + ROM[560]= 64'h0000000000000000; + ROM[561]= 64'h0000000000000000; + ROM[562]= 64'h0000000000000000; + ROM[563]= 64'h0000000000000000; + ROM[564]= 64'h0000000000000000; + ROM[565]= 64'h0000000000000000; + ROM[566]= 64'h0000000000000000; + ROM[567]= 64'h0000000000000000; + ROM[568]= 64'h0000000000000000; + ROM[569]= 64'h0000000000000000; + ROM[570]= 64'h0000000000000000; + ROM[571]= 64'h0000000000000000; + ROM[572]= 64'h0000000000000000; + ROM[573]= 64'h0000000000000000; + ROM[574]= 64'h0000000000000000; + ROM[575]= 64'h0000000000000000; + ROM[576]= 64'h0000000000000000; + ROM[577]= 64'h0000000000000000; + ROM[578]= 64'h0000000000000000; + ROM[579]= 64'h0000000000000000; + ROM[580]= 64'h0000000000000000; + ROM[581]= 64'h0000000000000000; + ROM[582]= 64'h0000000000000000; + ROM[583]= 64'h0000000000000000; + ROM[584]= 64'h0000000000000000; + ROM[585]= 64'h0000000000000000; + ROM[586]= 64'h0000000000000000; + ROM[587]= 64'h0000000000000000; + ROM[588]= 64'h0000000000000000; + ROM[589]= 64'h0000000000000000; + ROM[590]= 64'h0000000000000000; + ROM[591]= 64'h0000000000000000; + ROM[592]= 64'h0000000000000000; + ROM[593]= 64'h0000000000000000; + ROM[594]= 64'h0000000000000000; + ROM[595]= 64'h0000000000000000; + ROM[596]= 64'h0000000000000000; + ROM[597]= 64'h0000000000000000; + ROM[598]= 64'h0000000000000000; + ROM[599]= 64'h0000000000000000; + ROM[600]= 64'h0000000000000000; + ROM[601]= 64'h0000000000000000; + ROM[602]= 64'h0000000000000000; + ROM[603]= 64'h0000000000000000; + ROM[604]= 64'h0000000000000000; + ROM[605]= 64'h0000000000000000; + ROM[606]= 64'h0000000000000000; + ROM[607]= 64'h0000000000000000; + ROM[608]= 64'h0000000000000000; + ROM[609]= 64'h0000000000000000; + ROM[610]= 64'h0000000000000000; + ROM[611]= 64'h0000000000000000; + ROM[612]= 64'h0000000000000000; + ROM[613]= 64'h0000000000000000; + ROM[614]= 64'h0000000000000000; + ROM[615]= 64'h0000000000000000; + ROM[616]= 64'h0000000000000000; + ROM[617]= 64'h0000000000000000; + ROM[618]= 64'h0000000000000000; + ROM[619]= 64'h0000000000000000; + ROM[620]= 64'h0000000000000000; + ROM[621]= 64'h0000000000000000; + ROM[622]= 64'h0000000000000000; + ROM[623]= 64'h0000000000000000; + ROM[624]= 64'h0000000000000000; + ROM[625]= 64'h0000000000000000; + ROM[626]= 64'h0000000000000000; + ROM[627]= 64'h0000000000000000; + ROM[628]= 64'h0000000000000000; + ROM[629]= 64'h0000000000000000; + ROM[630]= 64'h0000000000000000; + ROM[631]= 64'h0000000000000000; + ROM[632]= 64'h0000000000000000; + ROM[633]= 64'h0000000000000000; + ROM[634]= 64'h0000000000000000; + ROM[635]= 64'h0000000000000000; + ROM[636]= 64'h0000000000000000; + ROM[637]= 64'h0000000000000000; + ROM[638]= 64'h0000000000000000; + ROM[639]= 64'h0000000000000000; + ROM[640]= 64'h00600100d2e3ca40; end end end diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 845a96c14..c58babb6f 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -56,7 +56,7 @@ module uncore ( input logic [31:0] GPIOPinsIn, // GPIO pin input value output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable input logic UARTSin, // UART serial input - output logic UARTSout, // UART serial output + output logic UARTSout // UART serial output /*output logic SDCCmdOut, // SD Card command output output logic SDCCmdOE, // SD Card command output enable input logic SDCCmdIn, // SD Card command input @@ -150,7 +150,8 @@ module uncore ( end else begin : uart assign UARTSout = 0; assign UARTIntr = 0; end - if (`SDC_SUPPORTED == 1) begin : sdc + /*if (`SDC_SUPPORTED == 1) begin : sdc + SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, // sdc interface @@ -158,11 +159,12 @@ module uncore ( // interrupt to PLIC .SDCIntM ); - /*end else begin : sdc + end else begin : sdc assign SDCCLK = 0; assign SDCCmdOut = 0; - assign SDCCmdOE = 0;*/ + assign SDCCmdOE = 0; end + */ // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) | diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 92dded7ad..4fd50a2fe 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -55,7 +55,7 @@ module wallypipelinedsoc ( output logic [31:0] GPIOPinsOut, // output values for GPIO output logic [31:0] GPIOPinsEn, // output enables for GPIO input logic UARTSin, // UART serial data input - output logic UARTSout, // UART serial data output + output logic UARTSout // UART serial data output /*input logic SDCCmdIn, // SDC Command input output logic SDCCmdOut, // SDC Command output output logic SDCCmdOE, // SDC Command output enable @@ -86,7 +86,7 @@ module wallypipelinedsoc ( .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, - .UARTSout, .MTIME_CLINT, + .UARTSout, .MTIME_CLINT /*.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK*/); end diff --git a/tests/custom/boot/Makefile b/tests/custom/boot/Makefile index 6dec9c797..8294f2375 100644 --- a/tests/custom/boot/Makefile +++ b/tests/custom/boot/Makefile @@ -16,7 +16,7 @@ OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) TARGETDIR := bin -TARGET := $(TARGETDIR)/fpga-test-sdc +TARGET := $(TARGETDIR)/boot ROOT := .. LIBRARY_DIRS := LIBRARY_FILES := @@ -24,7 +24,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -LINKER :=linker.x +LINKER :=$(ROOT)/linker1000.x AFLAGS =$(MARCH) $(MABI) -W diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c index f9fa2c0fe..c9b2c6451 100644 --- a/tests/custom/boot/boot.c +++ b/tests/custom/boot/boot.c @@ -1,3 +1,4 @@ +#include #include "boot.h" /* Card type flags (card_type) */ @@ -82,6 +83,8 @@ #define ERR_DATA_CRC 36 #define ERR_DATA_FIFO 37 #define ERR_BUF_ALIGNMENT 38 +#define FR_DISK_ERR 39 +#define FR_TIMEOUT 40 struct sdc_regs { volatile uint32_t argument; @@ -111,7 +114,9 @@ struct sdc_regs { volatile uint64_t dma_addres; }; -static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013100; +#define MAX_BLOCK_CNT 0x1000 + +static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; static int errno __attribute__((section(".bss"))); // static DSTATUS drv_status __attribute__((section(".bss"))); @@ -130,6 +135,8 @@ static const char * errno_to_str(void) { case ERR_DATA_CRC: return "Data CRC error"; case ERR_DATA_FIFO: return "Data FIFO error"; case ERR_BUF_ALIGNMENT: return "Bad buffer alignment"; + case FR_DISK_ERR: return "Disk error"; + case FR_TIMEOUT: return "Timeout"; } return "Unknown error code"; } @@ -285,7 +292,9 @@ static int ini_sd(void) { // This clock divider is meant to initialize the card at // 400kHz - regs->clock_divider = 0x7c; + + // 22MHz/400kHz = 55 (base 10) = 0x37 - 0x01 = 0x36 + regs->clock_divider = 0x36; regs->software_reset = 0; while (regs->software_reset) {} usleep(5000); @@ -335,7 +344,8 @@ static int ini_sd(void) { if (send_cmd(CMD7, rca << 16) < 0) return -1; /* Clock 25MHz */ - regs->clock_divider = 3; + // 22Mhz/2 = 11Mhz + regs->clock_divider = 1; usleep(10000); /* Bus width 1-bit */ @@ -365,7 +375,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { while (count > 0) { UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return RES_ERROR; + if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt) < 0) return 1; if (bcnt > 1 && send_cmd(CMD12, 0) < 0) return 1; sector += (card_type & CT_BLOCK) ? bcnt : bytes; count -= bcnt; diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h index ef620cda0..3dd7116a7 100644 --- a/tests/custom/boot/boot.h +++ b/tests/custom/boot/boot.h @@ -7,6 +7,9 @@ typedef unsigned char BYTE; /* char must be 8-bit */ typedef uint16_t WORD; /* 16-bit unsigned integer */ typedef uint32_t DWORD; /* 32-bit unsigned integer */ typedef uint64_t QWORD; /* 64-bit unsigned integer */ -typedef WORD WCHAR; +typedef WORD WCHAR; + +typedef QWORD LBA_t; #endif // WALLYBOOT +