diff --git a/pipelined/src/fpu/unpacking.sv b/pipelined/src/fpu/unpacking.sv index f64901a7c..6e3d3398d 100644 --- a/pipelined/src/fpu/unpacking.sv +++ b/pipelined/src/fpu/unpacking.sv @@ -23,33 +23,34 @@ module unpacking ( logic XExpZero, YExpZero, ZExpZero; // input exponent zero logic YExpMaxE, ZExpMaxE; // input exponent all 1s logic XDoubleNaN, YDoubleNaN, ZDoubleNaN; + logic [31:0] XFloat, YFloat, ZFloat; // Bottom half or NaN, if RV64 and not properly NaN boxed // Determine if number is NaN as double precision to check single precision NaN boxing - if (`XLEN==32) begin - assign XDoubleNaN = 1; - assign YDoubleNaN = 1; - assign ZDoubleNaN = 1; + if (`FLEN==32) begin + assign XFloat = X[31:0]; + assign XFloat = Y[31:0]; + assign XFloat = Z[31:0]; end else begin - assign XDoubleNaN = &X[62:52] & |X[51:0]; - assign YDoubleNaN = &Y[62:52] & |Y[51:0]; - assign ZDoubleNaN = &Z[62:52] & |Z[51:0]; + assign XFloat = &X[`FLEN-1:32] ? X[31:0] : 32'h7fc00000; + assign YFloat = &Y[`FLEN-1:32] ? Y[31:0] : 32'h7fc00000; + assign ZFloat = &Z[`FLEN-1:32] ? Z[31:0] : 32'h7fc00000; end - assign XSgnE = FmtE ? X[63] : X[31]; - assign YSgnE = FmtE ? Y[63] : Y[31]; - assign ZSgnE = FmtE ? Z[63] : Z[31]; + assign XSgnE = FmtE ? X[63] : XFloat[31]; + assign YSgnE = FmtE ? Y[63] : YFloat[31]; + assign ZSgnE = FmtE ? Z[63] : ZFloat[31]; - assign XExpE = FmtE ? X[62:52] : {X[30], {3{~X[30]&~XExpZero|XExpMaxE}}, X[29:23]}; - assign YExpE = FmtE ? Y[62:52] : {Y[30], {3{~Y[30]&~YExpZero|YExpMaxE}}, Y[29:23]}; - assign ZExpE = FmtE ? Z[62:52] : {Z[30], {3{~Z[30]&~ZExpZero|ZExpMaxE}}, Z[29:23]}; + assign XExpE = FmtE ? X[62:52] : {XFloat[30], {3{~XFloat[30]&~XExpZero|XExpMaxE}}, XFloat[29:23]}; + assign YExpE = FmtE ? Y[62:52] : {YFloat[30], {3{~YFloat[30]&~YExpZero|YExpMaxE}}, YFloat[29:23]}; + assign ZExpE = FmtE ? Z[62:52] : {ZFloat[30], {3{~ZFloat[30]&~ZExpZero|ZExpMaxE}}, ZFloat[29:23]}; - assign XFracE = FmtE ? X[51:0] : {X[22:0], 29'b0}; - assign YFracE = FmtE ? Y[51:0] : {Y[22:0], 29'b0}; - assign ZFracE = FmtE ? Z[51:0] : {Z[22:0], 29'b0}; + assign XFracE = FmtE ? X[51:0] : {XFloat[22:0], 29'b0}; + assign YFracE = FmtE ? Y[51:0] : {YFloat[22:0], 29'b0}; + assign ZFracE = FmtE ? Z[51:0] : {ZFloat[22:0], 29'b0}; - assign XExpNonzero = FmtE ? |X[62:52] : |X[30:23]; - assign YExpNonzero = FmtE ? |Y[62:52] : |Y[30:23]; - assign ZExpNonzero = FmtE ? |Z[62:52] : |Z[30:23]; + assign XExpNonzero = FmtE ? |X[62:52] : |XFloat[30:23]; + assign YExpNonzero = FmtE ? |Y[62:52] : |YFloat[30:23]; + assign ZExpNonzero = FmtE ? |Z[62:52] : |ZFloat[30:23]; assign XExpZero = ~XExpNonzero; assign YExpZero = ~YExpNonzero; @@ -63,16 +64,16 @@ module unpacking ( assign YManE = {YExpNonzero, YFracE}; assign ZManE = {ZExpNonzero, ZFracE}; - assign XExpMaxE = FmtE ? &X[62:52] : &X[30:23]; - assign YExpMaxE = FmtE ? &Y[62:52] : &Y[30:23]; - assign ZExpMaxE = FmtE ? &Z[62:52] : &Z[30:23]; + assign XExpMaxE = FmtE ? &X[62:52] : &XFloat[30:23]; + assign YExpMaxE = FmtE ? &Y[62:52] : &YFloat[30:23]; + assign ZExpMaxE = FmtE ? &Z[62:52] : &ZFloat[30:23]; assign XNormE = ~(XExpMaxE|XExpZero); // force single precision input to be a NaN if it isn't properly Nan Boxed - assign XNaNE = XExpMaxE & ~XFracZero | ~FmtE & ~XDoubleNaN; - assign YNaNE = YExpMaxE & ~YFracZero | ~FmtE & ~YDoubleNaN; - assign ZNaNE = ZExpMaxE & ~ZFracZero | ~FmtE & ~ZDoubleNaN; + assign XNaNE = XExpMaxE & ~XFracZero; + assign YNaNE = YExpMaxE & ~YFracZero; + assign ZNaNE = ZExpMaxE & ~ZFracZero; assign XSNaNE = XNaNE&~XFracE[51]; assign YSNaNE = YNaNE&~YFracE[51]; diff --git a/pipelined/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv index 784001424..5372652b2 100644 --- a/pipelined/src/ieu/extend.sv +++ b/pipelined/src/ieu/extend.sv @@ -47,11 +47,6 @@ module extend ( // Store Conditional: zero offset 3'b101: if (`A_SUPPORTED) ExtImmD = 0; else ExtImmD = undefined; - default: begin - ExtImmD = undefined; // undefined - // synthesis translate_off - $error("Invalid ImmSrcD in extend"); - // synthesis translate_on - end + default: ExtImmD = undefined; // undefined endcase endmodule diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index bb4bced06..66d554b3f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -49,21 +49,6 @@ string tvpaths[] = '{ "rv32a/WALLY-LRSC", "2110" }; -/* string imperas32mmu[] = '{ - `MYIMPERASTEST, - "rv32mmu/WALLY-MMU-SV32", "3000", - "rv32mmu/WALLY-PMP", "3000" - //"rv32mmu/WALLY-PMA", "3000" - }; - - string imperas64mmu[] = '{ - `MYIMPERASTEST, - "rv64mmu/WALLY-MMU-SV48", "3000", - "rv64mmu/WALLY-MMU-SV39", "3000", - "rv64mmu/WALLY-PMP", "3000" - //"rv64mmu/WALLY-PMA", "3000" - }; */ - // *** restore CSR tests from Imperas old string extra64i[] = '{ @@ -159,16 +144,16 @@ string imperas32f[] = '{ "rv32i_m/F/FCVT-WU-S-RNE-01", "002010", "rv32i_m/F/FCVT-WU-S-RTZ-01", "002010", "rv32i_m/F/FCVT-WU-S-RUP-01", "002010", - "rv32i_m/F/FDIV-S-DYN-RDN-01", "002010", - "rv32i_m/F/FDIV-S-DYN-RMM-01", "002010", - "rv32i_m/F/FDIV-S-DYN-RNE-01", "002010", - "rv32i_m/F/FDIV-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FDIV-S-DYN-RUP-01", "002010", - "rv32i_m/F/FDIV-S-RDN-01", "002010", - "rv32i_m/F/FDIV-S-RMM-01", "002010", - "rv32i_m/F/FDIV-S-RNE-01", "002010", - "rv32i_m/F/FDIV-S-RTZ-01", "002010", - "rv32i_m/F/FDIV-S-RUP-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RDN-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RMM-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RNE-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RTZ-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RUP-01", "002010", + // "rv32i_m/F/FDIV-S-RDN-01", "002010", + // "rv32i_m/F/FDIV-S-RMM-01", "002010", + // "rv32i_m/F/FDIV-S-RNE-01", "002010", + // "rv32i_m/F/FDIV-S-RTZ-01", "002010", + // "rv32i_m/F/FDIV-S-RUP-01", "002010", "rv32i_m/F/FEQ-S-01", "002010", "rv32i_m/F/FLE-S-01", "002010", "rv32i_m/F/FLT-S-01", "002010", @@ -230,16 +215,16 @@ string imperas32f[] = '{ "rv32i_m/F/FSGNJN-S-01", "002010", "rv32i_m/F/FSGNJ-S-01", "002010", "rv32i_m/F/FSGNJX-S-01", "002010", - "rv32i_m/F/FSQRT-S-DYN-RDN-01", "002010", - "rv32i_m/F/FSQRT-S-DYN-RMM-01", "002010", - "rv32i_m/F/FSQRT-S-DYN-RNE-01", "002010", - "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FSQRT-S-DYN-RUP-01", "002010", - "rv32i_m/F/FSQRT-S-RDN-01", "002010", - "rv32i_m/F/FSQRT-S-RMM-01", "002010", - "rv32i_m/F/FSQRT-S-RNE-01", "002010", - "rv32i_m/F/FSQRT-S-RTZ-01", "002010", - "rv32i_m/F/FSQRT-S-RUP-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RDN-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RMM-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RNE-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RUP-01", "002010", + // "rv32i_m/F/FSQRT-S-RDN-01", "002010", + // "rv32i_m/F/FSQRT-S-RMM-01", "002010", + // "rv32i_m/F/FSQRT-S-RNE-01", "002010", + // "rv32i_m/F/FSQRT-S-RTZ-01", "002010", + // "rv32i_m/F/FSQRT-S-RUP-01", "002010", "rv32i_m/F/FSUB-S-DYN-RDN-01", "002010", "rv32i_m/F/FSUB-S-DYN-RMM-01", "002010", "rv32i_m/F/FSUB-S-DYN-RNE-01", "002010", @@ -346,16 +331,16 @@ string imperas32f[] = '{ "rv64i_m/F/FCVT-WU-S-RNE-01", "002010", "rv64i_m/F/FCVT-WU-S-RTZ-01", "002010", "rv64i_m/F/FCVT-WU-S-RUP-01", "002010", - "rv64i_m/F/FDIV-S-DYN-RDN-01", "002010", - "rv64i_m/F/FDIV-S-DYN-RMM-01", "002010", - "rv64i_m/F/FDIV-S-DYN-RNE-01", "002010", - "rv64i_m/F/FDIV-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FDIV-S-DYN-RUP-01", "002010", - "rv64i_m/F/FDIV-S-RDN-01", "002010", - "rv64i_m/F/FDIV-S-RMM-01", "002010", - "rv64i_m/F/FDIV-S-RNE-01", "002010", - "rv64i_m/F/FDIV-S-RTZ-01", "002010", - "rv64i_m/F/FDIV-S-RUP-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RDN-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RMM-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RNE-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RTZ-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RUP-01", "002010", + // "rv64i_m/F/FDIV-S-RDN-01", "002010", + // "rv64i_m/F/FDIV-S-RMM-01", "002010", + // "rv64i_m/F/FDIV-S-RNE-01", "002010", + // "rv64i_m/F/FDIV-S-RTZ-01", "002010", + // "rv64i_m/F/FDIV-S-RUP-01", "002010", "rv64i_m/F/FEQ-S-01", "002010", "rv64i_m/F/FLE-S-01", "002010", "rv64i_m/F/FLT-S-01", "002010", @@ -417,16 +402,16 @@ string imperas32f[] = '{ "rv64i_m/F/FSGNJN-S-01", "002010", "rv64i_m/F/FSGNJ-S-01", "002010", "rv64i_m/F/FSGNJX-S-01", "002010", - "rv64i_m/F/FSQRT-S-DYN-RDN-01", "002010", - "rv64i_m/F/FSQRT-S-DYN-RMM-01", "002010", - "rv64i_m/F/FSQRT-S-DYN-RNE-01", "002010", - "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FSQRT-S-DYN-RUP-01", "002010", - "rv64i_m/F/FSQRT-S-RDN-01", "002010", - "rv64i_m/F/FSQRT-S-RMM-01", "002010", - "rv64i_m/F/FSQRT-S-RNE-01", "002010", - "rv64i_m/F/FSQRT-S-RTZ-01", "002010", - "rv64i_m/F/FSQRT-S-RUP-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RDN-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RMM-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RNE-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RUP-01", "002010", + // "rv64i_m/F/FSQRT-S-RDN-01", "002010", + // "rv64i_m/F/FSQRT-S-RMM-01", "002010", + // "rv64i_m/F/FSQRT-S-RNE-01", "002010", + // "rv64i_m/F/FSQRT-S-RTZ-01", "002010", + // "rv64i_m/F/FSQRT-S-RUP-01", "002010", "rv64i_m/F/FSUB-S-DYN-RDN-01", "002010", "rv64i_m/F/FSUB-S-DYN-RMM-01", "002010", "rv64i_m/F/FSUB-S-DYN-RNE-01", "002010", @@ -526,16 +511,16 @@ string imperas32f[] = '{ "rv64i_m/D/FCVT-WU-D-RNE-01", "002010", "rv64i_m/D/FCVT-WU-D-RTZ-01", "002010", "rv64i_m/D/FCVT-WU-D-RUP-01", "002010", - "rv64i_m/D/FDIV-D-DYN-RDN-01", "002010", - "rv64i_m/D/FDIV-D-DYN-RMM-01", "002010", - "rv64i_m/D/FDIV-D-DYN-RNE-01", "002010", - "rv64i_m/D/FDIV-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FDIV-D-DYN-RUP-01", "002010", - "rv64i_m/D/FDIV-D-RDN-01", "002010", - "rv64i_m/D/FDIV-D-RMM-01", "002010", - "rv64i_m/D/FDIV-D-RNE-01", "002010", - "rv64i_m/D/FDIV-D-RTZ-01", "002010", - "rv64i_m/D/FDIV-D-RUP-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RDN-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RMM-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RNE-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RTZ-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RUP-01", "002010", + // "rv64i_m/D/FDIV-D-RDN-01", "002010", + // "rv64i_m/D/FDIV-D-RMM-01", "002010", + // "rv64i_m/D/FDIV-D-RNE-01", "002010", + // "rv64i_m/D/FDIV-D-RTZ-01", "002010", + // "rv64i_m/D/FDIV-D-RUP-01", "002010", "rv64i_m/D/FEQ-D-01", "002010", "rv64i_m/D/FLD-01", "002520", "rv64i_m/D/FLE-D-01", "002010", @@ -598,16 +583,16 @@ string imperas32f[] = '{ "rv64i_m/D/FSGNJ-D-01", "002010", "rv64i_m/D/FSGNJN-D-01", "002010", "rv64i_m/D/FSGNJX-D-01", "002010", - "rv64i_m/D/FSQRT-D-DYN-RDN-01", "002010", - "rv64i_m/D/FSQRT-D-DYN-RMM-01", "002010", - "rv64i_m/D/FSQRT-D-DYN-RNE-01", "002010", - "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FSQRT-D-DYN-RUP-01", "002010", - "rv64i_m/D/FSQRT-D-RDN-01", "002010", - "rv64i_m/D/FSQRT-D-RMM-01", "002010", - "rv64i_m/D/FSQRT-D-RNE-01", "002010", - "rv64i_m/D/FSQRT-D-RTZ-01", "002010", - "rv64i_m/D/FSQRT-D-RUP-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RDN-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RMM-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RNE-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RUP-01", "002010", + // "rv64i_m/D/FSQRT-D-RDN-01", "002010", + // "rv64i_m/D/FSQRT-D-RMM-01", "002010", + // "rv64i_m/D/FSQRT-D-RNE-01", "002010", + // "rv64i_m/D/FSQRT-D-RTZ-01", "002010", + // "rv64i_m/D/FSQRT-D-RUP-01", "002010", "rv64i_m/D/FSUB-D-DYN-RDN-01", "002010", "rv64i_m/D/FSUB-D-DYN-RMM-01", "002010", "rv64i_m/D/FSUB-D-DYN-RNE-01", "002010", @@ -1063,13 +1048,13 @@ string imperas32f[] = '{ "rv64i_m/D/d_fcvt.d.l_b26-01", "2220", "rv64i_m/D/d_fcvt.d.lu_b25-01", "2110", "rv64i_m/D/d_fcvt.d.lu_b26-01", "2220", - // "rv64i_m/D/d_fcvt.d.s_b1-01", "2110", // trying to put doubles into a s -> d conversion? also says 0 -/-> 0 but rather 7ff800... .signature.output looks suspicious - // "rv64i_m/D/d_fcvt.d.s_b22-01", "2110", // ^ from here to.... - // "rv64i_m/D/d_fcvt.d.s_b23-01", "2110", - // "rv64i_m/D/d_fcvt.d.s_b24-01", "2110", - // "rv64i_m/D/d_fcvt.d.s_b27-01", "2110", - // "rv64i_m/D/d_fcvt.d.s_b28-01", "2110", - // "rv64i_m/D/d_fcvt.d.s_b29-01", "2110", // ....here + "rv64i_m/D/d_fcvt.d.s_b1-01", "2110", + "rv64i_m/D/d_fcvt.d.s_b22-01", "2110", + "rv64i_m/D/d_fcvt.d.s_b23-01", "2110", + "rv64i_m/D/d_fcvt.d.s_b24-01", "2110", + "rv64i_m/D/d_fcvt.d.s_b27-01", "2110", + "rv64i_m/D/d_fcvt.d.s_b28-01", "2110", + "rv64i_m/D/d_fcvt.d.s_b29-01", "2110", "rv64i_m/D/d_fcvt.d.w_b25-01", "2120", "rv64i_m/D/d_fcvt.d.w_b26-01", "2220", "rv64i_m/D/d_fcvt.d.wu_b25-01", "2110", @@ -1369,7 +1354,7 @@ string imperas32f[] = '{ "rv32i_m/F/fnmsub_b17-01", "39d0", "rv32i_m/F/fnmsub_b18-01", "4d10", "rv32i_m/F/fnmsub_b2-01", "4d60", - //"rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile + "rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile "rv32i_m/F/fnmsub_b4-01", "3700", "rv32i_m/F/fnmsub_b5-01", "3ac0", "rv32i_m/F/fnmsub_b6-01", "3700",