Switch to out of tree riscv-arch-test with VM tests + add pmp & vm tests to testbench

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit cd94912fed2aab75d7d5f115b441da0813fdce8d
+Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca

testbench/testbench.sv

@@ -175,6 +175,7 @@ module testbench;
         "arch64zknd":    if (P.ZKND_SUPPORTED)    tests = arch64zknd;
         "arch64zkne":    if (P.ZKNE_SUPPORTED)    tests = arch64zkne;
         "arch64zknh":    if (P.ZKNH_SUPPORTED)    tests = arch64zknh;
+        "arch64pmp":     if (P.PMP_ENTRIES > 0)   tests = arch64pmp;
       endcase
     end else begin // RV32
       case (TEST)
@@ -217,6 +218,8 @@ module testbench;
         "arch32zknd":    if (P.ZKND_SUPPORTED)    tests = arch32zknd;
         "arch32zkne":    if (P.ZKNE_SUPPORTED)    tests = arch32zkne;
         "arch32zknh":    if (P.ZKNH_SUPPORTED)    tests = arch32zknh;
+        "arch32pmp":     if (P.PMP_ENTRIES > 0)   tests = arch32pmp;
+        "arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32;
       endcase
     end
     if (tests.size() == 0 & ElfFile == "none") begin

testbench/tests.vh

@@ -149,6 +149,121 @@ string wally32a_lrsc[] = '{
   "rv32i_m/privilege/src/WALLY-lrsc-01.S"
 };
 
+string arch32pmp[] = '{
+  `RISCVARCHTEST,
+  "rv32i_m/pmp32/src/pmp-CFG-reg.S",
+  "rv32i_m/pmp32/src/pmp-CSR-access.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RWX.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RWX.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RWX.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X.S"
+};
+
+string arch64pmp[] = '{
+  `RISCVARCHTEST,
+  "rv64i_m/pmp64/pmp64-CFG-reg.S",
+  "rv64i_m/pmp64/pmp64-CSR-access.S",
+  "rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-R-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-R.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW.S",
+  "rv64i_m/pmp64/pmp64-NA4-RWX.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX.S",
+  "rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-X-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-X.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RWX.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X.S",
+  "rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-R-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-R.S",
+  "rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S",
+  "rv64i_m/pmp64/pmp64-TOR-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-RW.S",
+  "rv64i_m/pmp64/pmp64-TOR-RWX.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX.S",
+  "rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-X-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-X.S"
+};
+
+string arch32vm_sv32[] = '{
+  `RISCVARCHTEST,
+  "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S"
+};
+
 string arch64priv[] = '{
   `RISCVARCHTEST,
   "rv64i_m/privilege/src/ebreak.S",

tests/riscof/sail_cSim/riscof_sail_cSim.py

@@ -52,7 +52,7 @@ class sail_cSim(pluginTemplate):
         ispec = utils.load_yaml(isa_yaml)['hart0']
         self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
         self.isa = 'rv' + self.xlen
-        self.sailargs = ' '
+        self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration
         self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
         if "I" in ispec["ISA"]:
             self.isa += 'i'
@@ -103,7 +103,6 @@ class sail_cSim(pluginTemplate):
 
             execute = "@cd "+testentry['work_dir']+";"
 
-#            cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf
             cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf
             compile_cmd = cmd + ' -D' + " -D".join(testentry['macros'])
             execute+=compile_cmd+";"
@@ -117,8 +116,7 @@ class sail_cSim(pluginTemplate):
                 reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
                 execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying
             else:
-                execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
+                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step  ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
-#                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
 
             cov_str = ' '
             for label in testentry['coverage_labels']:

tests/riscof/spike/spike_rv32gc_isa.yaml

@@ -26,4 +26,4 @@ hart0:
               legal:
                 - extensions[25:0] bitmask [0x000112D, 0x0000000]
               wr_illegal:
-                - Unchangedcd 
+                - Unchanged