diff --git a/README.md b/README.md index 400df6b3b..32e363569 100644 --- a/README.md +++ b/README.md @@ -125,7 +125,7 @@ Note: make --jobs will reduce compile time by compiling in parallel. However, a We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with: $ cd $RISCV - $ export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH + $ export PATH=$RISCV/bin:$PATH $ git clone https://github.com/sifive/elf2hex.git $ cd elf2hex $ autoreconf -i diff --git a/synthDC/Makefile b/synthDC/Makefile index 974626706..76531d950 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -84,22 +84,22 @@ endif endif # adjust config if synthesizing with any modifications -ifeq ($(MOD), FPUoff) +ifneq ($(MOD), orig) + # PMP 0 + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh +ifneq ($(MOD), PMP0) + # no priv + sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh +ifneq ($(MOD), noPriv) # turn off FPU sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/wally-config.vh sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/wally-config.vh -else ifeq ($(MOD), PMP16) - # PMP 16 - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/wally-config.vh -else ifeq ($(MOD), PMP0) - # PMP 0 - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh -else ifeq ($(MOD), noMulDiv) +ifneq ($(MOD), noFPU) # no muldiv sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh -else ifeq ($(MOD), noPriv) - # no priv - sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh +endif +endif +endif endif ifeq ($(SAIFPOWER), 1) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 430f86178..3d939644a 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -8,6 +8,7 @@ from matplotlib.cbook import flatten import matplotlib.pyplot as plt import matplotlib.lines as lines import numpy as np +from adjustText import adjust_text from ppa.ppaAnalyze import noOutliers from matplotlib import ticker import argparse @@ -149,9 +150,8 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False): ax.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}')) - for i in range(len(labels)): - plt.annotate(labels[i], (delays[i], areas[i]), textcoords="offset points", xytext=(0,10), ha='center') - + texts = [plt.text(delays[i], areas[i], labels[i], ha='center', va='center') for i in range(len(labels))] + adjust_text(texts) return fig @@ -169,7 +169,7 @@ def plotFeatures(tech, width, config): fig = areaDelay(tech, delays, areas, labels, fig, ax) - titlestr = tech+'_'+width+config + titlestr = tech+'_'+width+config+'_'+str(freq)+'MHz' plt.title(titlestr) plt.savefig(final_directory + '/features_'+titlestr+'.png') @@ -240,8 +240,8 @@ def addFO4axis(fig, ax, tech): if __name__ == '__main__': parser = argparse.ArgumentParser() - parser.add_argument("-s", "--skyfreq", type=int, default=3000, help = "Target frequency used for sky90 syntheses") - parser.add_argument("-t", "--tsmcfreq", type=int, default=10000, help = "Target frequency used for tsmc28 syntheses") + parser.add_argument("-s", "--skyfreq", type=int, default=1500, help = "Target frequency used for sky90 syntheses") + parser.add_argument("-t", "--tsmcfreq", type=int, default=5000, help = "Target frequency used for tsmc28 syntheses") args = parser.parse_args() TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy") diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 3c96c38ee..3253607d5 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -37,8 +37,6 @@ if __name__ == '__main__': args = parser.parse_args() tech = args.tech if args.tech else 'sky90' - defaultfreq = 3000 if tech == 'sky90' else 10000 - freq = args.targetfreq if args.targetfreq else defaultfreq maxopt = int(args.maxopt) usesram = int(args.usesram) mod = 'orig' @@ -49,12 +47,18 @@ if __name__ == '__main__': for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep runSynth(config, mod, tech, freq, maxopt, usesram) if args.configsweep: + defaultfreq = 1500 if tech == 'sky90' else 5000 + freq = args.targetfreq if args.targetfreq else defaultfreq for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs runSynth(config, mod, tech, freq, maxopt, usesram) if args.featuresweep: + defaultfreq = 500 if tech == 'sky90' else 1500 + freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' - for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', + for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: runSynth(config, mod, tech, freq, maxopt, usesram) else: + defaultfreq = 500 if tech == 'sky90' else 1500 + freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' runSynth(config, mod, tech, freq, maxopt, usesram) \ No newline at end of file