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pipelining of fetch into evict AHB requests.

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This commit is contained in:
Ross Thompson 2022-09-13 16:19:10 -05:00
parent 40e7d2648f
commit 2ae62c2869
2 changed files with 14 additions and 8 deletions
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2
pipelined/src/cache/cachefsm.sv vendored
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@ -197,7 +197,7 @@ module cachefsm
assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck); assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck);
assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
(CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
(CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) |
(CurrState == STATE_FLUSH_CHECK & VictimDirty); (CurrState == STATE_FLUSH_CHECK & VictimDirty);
// **** can this be simplified? // **** can this be simplified?
assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.

20
pipelined/src/ebu/buscachefsm.sv
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@ -91,10 +91,14 @@ module buscachefsm #(parameter integer WordCountThreshold,
else NextState = DATA_PHASE; else NextState = DATA_PHASE;
MEM3: if(CPUBusy) NextState = MEM3; MEM3: if(CPUBusy) NextState = MEM3;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
CACHE_FETCH: if(HREADY & FinalWordCount) NextState = ADR_PHASE; CACHE_FETCH: if(HREADY & FinalWordCount & CacheRW[0]) NextState = CACHE_EVICT;
else NextState = CACHE_FETCH; else if(HREADY & FinalWordCount & CacheRW[1]) NextState = CACHE_FETCH;
CACHE_EVICT: if(HREADY & FinalWordCount) NextState = ADR_PHASE; else if(HREADY & FinalWordCount & ~|CacheRW) NextState = ADR_PHASE;
else NextState = CACHE_EVICT; else NextState = CACHE_FETCH;
CACHE_EVICT: if(HREADY & FinalWordCount & CacheRW[0]) NextState = CACHE_EVICT;
else if(HREADY & FinalWordCount & CacheRW[1]) NextState = CACHE_FETCH;
else if(HREADY & FinalWordCount & ~|CacheRW) NextState = ADR_PHASE;
else NextState = CACHE_EVICT;
default: NextState = ADR_PHASE; default: NextState = ADR_PHASE;
endcase endcase
end end
@ -136,7 +140,8 @@ module buscachefsm #(parameter integer WordCountThreshold,
// AHB bus interface // AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|RW | |CacheRW)) | assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|RW | |CacheRW)) |
(CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : (CurrState == DATA_PHASE & ~HREADY) |
(CacheAccess & ~|WordCount & |CacheRW) ? AHB_NONSEQ :
(CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
assign HWRITE = RW[0] | CacheRW[0]; assign HWRITE = RW[0] | CacheRW[0];
@ -155,7 +160,8 @@ module buscachefsm #(parameter integer WordCountThreshold,
// communication to cache // communication to cache
assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount); assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount);
assign SelBusWord = (CurrState == ADR_PHASE & (RW[0] | CacheRW[0])) | assign SelBusWord = (CurrState == ADR_PHASE & (RW[0] | CacheRW[0])) |
(CurrState == DATA_PHASE & RW[0]) | (CurrState == DATA_PHASE & RW[0]) |
(CurrState == CACHE_EVICT); (CurrState == CACHE_EVICT) |
(CurrState == CACHE_FETCH);
endmodule endmodule