From d5ec797ba467331f702339234565d656577f21d8 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 7 Jun 2021 09:46:52 -0400
Subject: [PATCH] Refactored configuration files and renamed testbench-busybear
to testbench-linux
---
.../config/buildroot/wally-config.vh | 24 +-
.../config/busybear/wally-config.vh | 24 +-
.../config/coremark-64i/wally-config.vh | 21 +-
.../config/coremark/wally-config.vh | 19 +-
.../config/coremark_bare/wally-config.vh | 24 +-
wally-pipelined/config/rv32ic/wally-config.vh | 20 +-
wally-pipelined/config/rv64BP/wally-config.vh | 22 +-
wally-pipelined/config/rv64ic/wally-config.vh | 22 +-
.../config/rv64icfd/wally-config.vh | 19 +-
.../config/rv64imc/wally-config.vh | 22 +-
.../config/shared/wally-constants.vh | 22 +-
wally-pipelined/config/shared/wally-shared.vh | 44 ++
wally-pipelined/lint-wally | 2 +-
.../regression/wally-buildroot-batch.do | 2 +-
wally-pipelined/regression/wally-buildroot.do | 2 +-
.../regression/wally-busybear-batch.do | 2 +-
wally-pipelined/regression/wally-busybear.do | 2 +-
wally-pipelined/src/mmu/cam_line.sv | 2 +-
wally-pipelined/src/mmu/page_number_mixer.sv | 1 -
wally-pipelined/src/mmu/pagetablewalker.sv | 3 +-
wally-pipelined/src/mmu/tlb.sv | 1 -
wally-pipelined/src/mmu/tlb_cam.sv | 2 +-
wally-pipelined/src/mmu/tlb_ram.sv | 1 -
wally-pipelined/src/privileged/pmpadrdec.sv | 1 -
.../src/wally/wallypipelinedhart.sv | 1 -
.../testbench/testbench-busybear.sv | 18 +-
wally-pipelined/testbench/testbench-linux.sv | 735 ++++++++++++++++++
27 files changed, 835 insertions(+), 223 deletions(-)
create mode 100644 wally-pipelined/config/shared/wally-shared.vh
create mode 100644 wally-pipelined/testbench/testbench-linux.sv
diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh
index 57740b687..679175f09 100644
--- a/wally-pipelined/config/buildroot/wally-config.vh
+++ b/wally-pipelined/config/buildroot/wally-config.vh
@@ -24,31 +24,20 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
`define BUILDROOT 1
`define BUSYBEAR 0
-`define BUSYBEAR_FIX_READ {'h10000005}
-`define BUSYBEAR_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
+`define LINUX_FIX_READ {'h10000005}
+`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
`define MISA (32'h0014112D)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define ZCOUNTERS_SUPPORTED 1
`define COUNTERS 31
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
@@ -100,9 +89,6 @@
`define PLIC_NUM_SRC 53
`define PLIC_UART_ID 4
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-
`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
`define BPRED_ENABLED 1
diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index a840676df..ddcc70207 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -24,31 +24,20 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
`define BUILDROOT 0
`define BUSYBEAR 1
-`define BUSYBEAR_FIX_READ {'h10000005}
-`define BUSYBEAR_TEST_VECTORS "/courses/e190ax/busybear_boot/"
+`define LINUX_FIX_READ {'h10000005}
+`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
`define MISA (32'h0014112D)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define ZCOUNTERS_SUPPORTED 1
`define COUNTERS 31
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
@@ -101,9 +90,6 @@
`define PLIC_NUM_SRC 53
`define PLIC_UART_ID 4
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-
`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
diff --git a/wally-pipelined/config/coremark-64i/wally-config.vh b/wally-pipelined/config/coremark-64i/wally-config.vh
index 367289943..9c54b38b7 100644
--- a/wally-pipelined/config/coremark-64i/wally-config.vh
+++ b/wally-pipelined/config/coremark-64i/wally-config.vh
@@ -24,27 +24,16 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 64
//`define MISA (32'h00000104)
`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define ZCOUNTERS_SUPPORTED 1
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
@@ -83,7 +72,3 @@
// Hardware configuration
`define UART_PRESCALE 1
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh
index 47e9c7319..34c8cae6a 100644
--- a/wally-pipelined/config/coremark/wally-config.vh
+++ b/wally-pipelined/config/coremark/wally-config.vh
@@ -24,6 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
`define BUILDROOT 0
`define BUSYBEAR 0
@@ -32,13 +35,6 @@
//`define MISA (32'h00000104)
`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1
@@ -46,10 +42,6 @@
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
-
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
@@ -100,11 +92,6 @@
// Can add PLIC Config here
// Num interrupt sources
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
-
`define TWO_BIT_PRELOAD "../config/coremark/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/coremark/BTBPredictor.txt"
`define BPRED_ENABLED 1
diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh
index b42dd678d..144f472b5 100644
--- a/wally-pipelined/config/coremark_bare/wally-config.vh
+++ b/wally-pipelined/config/coremark_bare/wally-config.vh
@@ -24,6 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
`define BUILDROOT 0
`define BUSYBEAR 0
@@ -32,23 +35,9 @@
//`define MISA (32'h00000104)
`define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
@@ -101,12 +90,7 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
-
-`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
+/`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE"//comments
diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh
index 17daa5722..c27b5e31d 100644
--- a/wally-pipelined/config/rv32ic/wally-config.vh
+++ b/wally-pipelined/config/rv32ic/wally-config.vh
@@ -24,6 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
`define BUILDROOT 0
`define BUSYBEAR 0
@@ -31,23 +34,9 @@
`define XLEN 32
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
@@ -100,9 +89,6 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
`define BPRED_ENABLED 1
diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh
index f85e0c228..41dc3ff08 100644
--- a/wally-pipelined/config/rv64BP/wally-config.vh
+++ b/wally-pipelined/config/rv64BP/wally-config.vh
@@ -24,6 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
// RV32 or RV64: XLEN = 32 or 64
`define BUILDROOT 0
`define BUSYBEAR 0
@@ -33,23 +36,9 @@
//`define MISA (32'h00000105)
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
@@ -102,11 +91,6 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
-
`define TWO_BIT_PRELOAD "../config/rv64BP/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64BP/BTBPredictor.txt"
`define BPRED_ENABLED 1
diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index 12d254ba8..662227272 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -24,6 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
`define BUILDROOT 0
`define BUSYBEAR 0
@@ -32,23 +35,9 @@
// MISA RISC-V configuration per specification
`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
@@ -101,11 +90,6 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
-
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
`define BPRED_ENABLED 1
diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh
index 4b0ce324b..46129f16a 100644
--- a/wally-pipelined/config/rv64icfd/wally-config.vh
+++ b/wally-pipelined/config/rv64icfd/wally-config.vh
@@ -24,6 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
`define BUILDROOT 0
`define BUSYBEAR 0
@@ -32,13 +35,6 @@
// MISA RISC-V configuration per specification
`define MISA (32'h00000104 | 0 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1
@@ -46,10 +42,6 @@
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
-
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
@@ -102,11 +94,6 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
-
`define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt"
`define BPRED_ENABLED 1
diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh
index 8c42cd81c..0d4cfeb04 100644
--- a/wally-pipelined/config/rv64imc/wally-config.vh
+++ b/wally-pipelined/config/rv64imc/wally-config.vh
@@ -24,6 +24,9 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
+`include "wally-constants.vh"
+`include "wally-shared.vh"
+
`define BUILDROOT 0
`define BUSYBEAR 0
@@ -32,23 +35,9 @@
// MISA RISC-V configuration per specification
`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
// Microarchitectural Features
`define UARCH_PIPELINED 1
@@ -97,11 +86,6 @@
`define PLIC_NUM_SRC 53
`define PLIC_UART_ID 4
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
-
`define TWO_BIT_PRELOAD "../config/rv64imc/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64imc/BTBPredictor.txt"
`define BPRED_ENABLED 1
diff --git a/wally-pipelined/config/shared/wally-constants.vh b/wally-pipelined/config/shared/wally-constants.vh
index ec225f8c4..66691769e 100644
--- a/wally-pipelined/config/shared/wally-constants.vh
+++ b/wally-pipelined/config/shared/wally-constants.vh
@@ -28,24 +28,10 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
-`include "wally-config.vh"
-
-/*
-// Virtual Memory Constants (sv48)
-`define VPN_SEGMENT_BITS_RV64 9
-`define VPN_BITS_RV64 36
-`define PPN_HIGH_SEGMENT_BITS_RV64 17
-`define PPN_BITS_RV64 44
-`define PA_BITS_RV64 56
-`define SVMODE_BITS_RV64 4
-// Virtual Memory Constants (sv32)
-`define VPN_SEGMENT_BITS_RV32 10
-`define VPN_BITS_RV32 20
-`define PPN_HIGH_SEGMENT_BITS_RV32 12
-`define PPN_BITS_RV32 22
-`define PA_BITS_RV32 34
-`define SVMODE_BITS_RV32 1
-*/
+// Privileged modes
+`define M_MODE (2'b11)
+`define S_MODE (2'b01)
+`define U_MODE (2'b00)
// Virtual Memory Constants
`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
diff --git a/wally-pipelined/config/shared/wally-shared.vh b/wally-pipelined/config/shared/wally-shared.vh
new file mode 100644
index 000000000..eecdfa031
--- /dev/null
+++ b/wally-pipelined/config/shared/wally-shared.vh
@@ -0,0 +1,44 @@
+//////////////////////////////////////////
+// wally-shared.vh
+//
+// Written: david_harris@hmc.edu 7 June 2021
+//
+// Purpose: Shared and default configuration values common to all designs
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// macros to define supported modes
+
+`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
+`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
+`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
+`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
+`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
+`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
+`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
+
+// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
+//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
+`define N_SUPPORTED 0
+
+// Disable spurious Verilator warnings
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off WIDTH */
+/* verilator lint_off ASSIGNDLY */
+/* verilator lint_off PINCONNECTEMPTY */
diff --git a/wally-pipelined/lint-wally b/wally-pipelined/lint-wally
index d741d3687..5f63c6d3e 100755
--- a/wally-pipelined/lint-wally
+++ b/wally-pipelined/lint-wally
@@ -7,7 +7,7 @@ verilator=`which verilator`
basepath=$(dirname $0)
for config in rv64ic rv32ic; do
echo "$config linting..."
- if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/$config" $basepath/src/*/*.sv); then
+ if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi
diff --git a/wally-pipelined/regression/wally-buildroot-batch.do b/wally-pipelined/regression/wally-buildroot-batch.do
index a2535696d..32a1f114c 100644
--- a/wally-pipelined/regression/wally-buildroot-batch.do
+++ b/wally-pipelined/regression/wally-buildroot-batch.do
@@ -26,7 +26,7 @@ vlib work-buildroot
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
-vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583
# start and run simulation
diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do
index 30a443d14..c212831e8 100644
--- a/wally-pipelined/regression/wally-buildroot.do
+++ b/wally-pipelined/regression/wally-buildroot.do
@@ -26,7 +26,7 @@ vlib work-busybear
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
-vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583
# start and run simulation
diff --git a/wally-pipelined/regression/wally-busybear-batch.do b/wally-pipelined/regression/wally-busybear-batch.do
index 5d9b44ca8..a4a80eb74 100644
--- a/wally-pipelined/regression/wally-busybear-batch.do
+++ b/wally-pipelined/regression/wally-busybear-batch.do
@@ -26,7 +26,7 @@ vlib work_busybear
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
-vlog -work work_busybear +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
+vlog -work work_busybear +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583
# start and run simulation
diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do
index 2d522c606..3638a7755 100644
--- a/wally-pipelined/regression/wally-busybear.do
+++ b/wally-pipelined/regression/wally-busybear.do
@@ -26,7 +26,7 @@ vlib work-busybear
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
-vlog +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583
# start and run simulation
diff --git a/wally-pipelined/src/mmu/cam_line.sv b/wally-pipelined/src/mmu/cam_line.sv
index 6bab0b60b..47ab490c7 100644
--- a/wally-pipelined/src/mmu/cam_line.sv
+++ b/wally-pipelined/src/mmu/cam_line.sv
@@ -26,7 +26,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
-`include "wally-constants.vh"
+`include "wally-config.vh"
module cam_line #(parameter KEY_BITS = 20,
parameter HIGH_SEGMENT_BITS = 10) (
diff --git a/wally-pipelined/src/mmu/page_number_mixer.sv b/wally-pipelined/src/mmu/page_number_mixer.sv
index 03851018d..7f09dff58 100644
--- a/wally-pipelined/src/mmu/page_number_mixer.sv
+++ b/wally-pipelined/src/mmu/page_number_mixer.sv
@@ -29,7 +29,6 @@
///////////////////////////////////////////
`include "wally-config.vh"
-`include "wally-constants.vh"
module page_number_mixer #(parameter BITS = 20,
parameter HIGH_SEGMENT_BITS = 10) (
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index b0e4fe8e5..725a319d4 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -28,11 +28,10 @@
///////////////////////////////////////////
`include "wally-config.vh"
-`include "wally-constants.vh"
/* ***
TO-DO:
- - Implement better accessed/dirty behavior
+ - Implement faults on accessed/dirty behavior
*/
module pagetablewalker (
diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv
index 1828c98e7..3508f9576 100644
--- a/wally-pipelined/src/mmu/tlb.sv
+++ b/wally-pipelined/src/mmu/tlb.sv
@@ -47,7 +47,6 @@
*/
`include "wally-config.vh"
-`include "wally-constants.vh"
// The TLB will have 2**ENTRY_BITS total entries
module tlb #(parameter ENTRY_BITS = 3,
diff --git a/wally-pipelined/src/mmu/tlb_cam.sv b/wally-pipelined/src/mmu/tlb_cam.sv
index 78d9ff8d3..160e61551 100644
--- a/wally-pipelined/src/mmu/tlb_cam.sv
+++ b/wally-pipelined/src/mmu/tlb_cam.sv
@@ -26,7 +26,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
-`include "wally-constants.vh"
+`include "wally-config.vh"
module tlb_cam #(parameter ENTRY_BITS = 3,
parameter KEY_BITS = 20,
diff --git a/wally-pipelined/src/mmu/tlb_ram.sv b/wally-pipelined/src/mmu/tlb_ram.sv
index 9c281d2d8..a44e16b47 100644
--- a/wally-pipelined/src/mmu/tlb_ram.sv
+++ b/wally-pipelined/src/mmu/tlb_ram.sv
@@ -26,7 +26,6 @@
///////////////////////////////////////////
`include "wally-config.vh"
-`include "wally-constants.vh"
module tlb_ram #(parameter ENTRY_BITS = 3) (
input clk, reset,
diff --git a/wally-pipelined/src/privileged/pmpadrdec.sv b/wally-pipelined/src/privileged/pmpadrdec.sv
index 1e2a14a1a..f9e86cdc7 100644
--- a/wally-pipelined/src/privileged/pmpadrdec.sv
+++ b/wally-pipelined/src/privileged/pmpadrdec.sv
@@ -28,7 +28,6 @@
///////////////////////////////////////////
`include "wally-config.vh"
-`include "wally-constants.vh"
module pmpadrdec (
input logic [31:0] HADDR,
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index aa252e377..c1b16d668 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -24,7 +24,6 @@
///////////////////////////////////////////
`include "wally-config.vh"
-`include "wally-constants.vh"
/* verilator lint_on UNUSED */
module wallypipelinedhart (
diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index 9d150731e..824188fd1 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -109,7 +109,7 @@ module testbench();
// read pc trace file
integer data_file_PC, scan_file_PC;
initial begin
- data_file_PC = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r");
+ data_file_PC = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r");
if (data_file_PC == 0) begin
$display("file couldn't be opened");
$stop;
@@ -118,7 +118,7 @@ module testbench();
integer data_file_PCW, scan_file_PCW;
initial begin
- data_file_PCW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r");
+ data_file_PCW = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r");
if (data_file_PCW == 0) begin
$display("file couldn't be opened");
$stop;
@@ -128,7 +128,7 @@ module testbench();
// read register trace file
integer data_file_rf, scan_file_rf;
initial begin
- data_file_rf = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedRegs.txt"}, "r");
+ data_file_rf = $fopen({`LINUX_TEST_VECTORS,"parsedRegs.txt"}, "r");
if (data_file_rf == 0) begin
$display("file couldn't be opened");
$stop;
@@ -138,7 +138,7 @@ module testbench();
// read CSR trace file
integer data_file_csr, scan_file_csr;
initial begin
- data_file_csr = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedCSRs2.txt"}, "r");
+ data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs2.txt"}, "r");
if (data_file_csr == 0) begin
$display("file couldn't be opened");
$stop;
@@ -148,7 +148,7 @@ module testbench();
// read memreads trace file
integer data_file_memR, scan_file_memR;
initial begin
- data_file_memR = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemRead.txt"}, "r");
+ data_file_memR = $fopen({`LINUX_TEST_VECTORS,"parsedMemRead.txt"}, "r");
if (data_file_memR == 0) begin
$display("file couldn't be opened");
$stop;
@@ -158,7 +158,7 @@ module testbench();
// read memwrite trace file
integer data_file_memW, scan_file_memW;
initial begin
- data_file_memW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemWrite.txt"}, "r");
+ data_file_memW = $fopen({`LINUX_TEST_VECTORS,"parsedMemWrite.txt"}, "r");
if (data_file_memW == 0) begin
$display("file couldn't be opened");
$stop;
@@ -167,8 +167,8 @@ module testbench();
// initial loading of memories
initial begin
- $readmemh({`BUSYBEAR_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
- $readmemh({`BUSYBEAR_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
+ $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
+ $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
end
@@ -279,7 +279,7 @@ module testbench();
`ERROR
end
if ((readMask & HRDATA) !== (readMask & dut.HRDATA)) begin
- if (HADDR inside `BUSYBEAR_FIX_READ) begin
+ if (HADDR inside `LINUX_FIX_READ) begin
//$display("warning %0t ps, instr %0d, adr %0d: forcing HRDATA to expected: %x, %x", $time, instrs, HADDR, HRDATA, dut.HRDATA);
force dut.uncore.HRDATA = HRDATA;
#9;
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
new file mode 100644
index 000000000..52c40060c
--- /dev/null
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -0,0 +1,735 @@
+///////////////////////////////////////////
+// testbench-linux.sv
+//
+// Written: nboorstin@g.hmc.edu 2021
+// Modified:
+//
+// Purpose: Testbench for buildroot or busybear linux
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module testbench();
+ logic clk, reset;
+ logic [31:0] GPIOPinsIn;
+ logic [31:0] GPIOPinsOut, GPIOPinsEn;
+
+ // instantiate device to be tested
+ logic [31:0] CheckInstrD;
+
+ logic [`AHBW-1:0] HRDATA;
+ logic [31:0] HADDR;
+ logic [`AHBW-1:0] HWDATA;
+ logic HWRITE;
+ logic [2:0] HSIZE;
+ logic [2:0] HBURST;
+ logic [3:0] HPROT;
+ logic [1:0] HTRANS;
+ logic HMASTLOCK;
+ logic HCLK, HRESETn;
+ logic [`AHBW-1:0] HRDATAEXT;
+ logic HREADYEXT, HRESPEXT;
+ logic UARTSout;
+
+ assign GPIOPinsIn = 0;
+ assign UARTSin = 1;
+
+ // instantiate processor and memories
+ wallypipelinedsoc dut(.*);
+
+ /**
+ * Walk the page table stored in dtim according to sv39 logic and translate a
+ * virtual address to a physical address.
+ *
+ * See section 4.3.2 of the RISC-V Privileged specification for a full
+ * explanation of the below algorithm.
+ */
+ function logic [`XLEN-1:0] adrTranslator(
+ input logic [`XLEN-1:0] adrIn);
+ begin
+ logic SvMode, PTE_R, PTE_X;
+ logic [`XLEN-1:0] SATP, PTE;
+ logic [55:0] BaseAdr, PAdr;
+ logic [8:0] VPN [0:2];
+ logic [11:0] Offset;
+
+ int i;
+
+ // Grab the SATP register from privileged unit
+ SATP = dut.hart.priv.csr.SATP_REGW;
+
+ // Split the virtual address into page number segments and offset
+ VPN[2] = adrIn[38:30];
+ VPN[1] = adrIn[29:21];
+ VPN[0] = adrIn[20:12];
+ Offset = adrIn[11:0];
+
+ // We do not support sv48; only sv39
+ SvMode = SATP[63];
+
+ // Only perform translation if translation is on and the processor is not
+ // in machine mode
+ if (SvMode && (dut.hart.priv.PrivilegeModeW != `M_MODE)) begin
+ BaseAdr = SATP[43:0] << 12;
+
+ for (i = 2; i >= 0; i--) begin
+ PAdr = BaseAdr + (VPN[i] << 3);
+
+ // dtim.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
+ // by 3 (the PTE size) to get the requested 64-bit PTE.
+ PTE = dut.uncore.dtim.RAM[PAdr >> 3];
+ PTE_R = PTE[1];
+ PTE_X = PTE[3];
+ if (PTE_R || PTE_X) begin
+ // Leaf page found
+ break;
+ end else begin
+ // Go to next level of table
+ BaseAdr = PTE[53:10] << 12;
+ end
+ end
+
+ // Determine which parts of the PTE page number to use based on the
+ // level of the page table we reached.
+ if (i == 2) begin
+ // Gigapage
+ assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset};
+ end else if (i == 1) begin
+ // Megapage
+ assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset};
+ end else begin
+ // Kilopage
+ assign adrTranslator = {8'b0, PTE[53:10], Offset};
+ end
+ end else begin
+ // Direct translation if address translation is not on
+ assign adrTranslator = adrIn;
+ end
+ end
+ endfunction
+
+ // initialize test
+ initial
+ begin
+ reset <= 1; # 22; reset <= 0;
+ end
+
+ // read pc trace file
+ integer data_file_PC, scan_file_PC;
+ initial begin
+ data_file_PC = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r");
+ if (data_file_PC == 0) begin
+ $display("file couldn't be opened");
+ $stop;
+ end
+ end
+
+ integer data_file_PCW, scan_file_PCW;
+ initial begin
+ data_file_PCW = $fopen({`LINUX_TEST_VECTORS,"parsedPC.txt"}, "r");
+ if (data_file_PCW == 0) begin
+ $display("file couldn't be opened");
+ $stop;
+ end
+ end
+
+ // read register trace file
+ integer data_file_rf, scan_file_rf;
+ initial begin
+ data_file_rf = $fopen({`LINUX_TEST_VECTORS,"parsedRegs.txt"}, "r");
+ if (data_file_rf == 0) begin
+ $display("file couldn't be opened");
+ $stop;
+ end
+ end
+
+ // read CSR trace file
+ integer data_file_csr, scan_file_csr;
+ initial begin
+ data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs2.txt"}, "r");
+ if (data_file_csr == 0) begin
+ $display("file couldn't be opened");
+ $stop;
+ end
+ end
+
+ // read memreads trace file
+ integer data_file_memR, scan_file_memR;
+ initial begin
+ data_file_memR = $fopen({`LINUX_TEST_VECTORS,"parsedMemRead.txt"}, "r");
+ if (data_file_memR == 0) begin
+ $display("file couldn't be opened");
+ $stop;
+ end
+ end
+
+ // read memwrite trace file
+ integer data_file_memW, scan_file_memW;
+ initial begin
+ data_file_memW = $fopen({`LINUX_TEST_VECTORS,"parsedMemWrite.txt"}, "r");
+ if (data_file_memW == 0) begin
+ $display("file couldn't be opened");
+ $stop;
+ end
+ end
+
+ // initial loading of memories
+ initial begin
+ $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
+ $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
+ $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
+ $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
+ end
+
+ integer warningCount = 0;
+ integer instrs;
+
+ //logic[63:0] adrTranslation[4:0];
+ //string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"};
+ //initial begin
+ // for(int i=0; i<5; i++) begin
+ // adrTranslation[i] = 64'b0;
+ // end
+ //end
+
+ //function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func);
+ // if (adr[11:0] !== adrExpected[11:0]) begin
+ // equal = 1'b0;
+ // end else begin
+ // equal = 1'b1;
+ // if ((adr+adrTranslation[func]) !== adrExpected) begin
+ // adrTranslation[func] = adrExpected - adr;
+ // $display("warning: probably new address translation %x for %s at instr %0d", adrTranslation[func], translationType[func], instrs);
+ // warningCount += 1;
+ // end
+ // end
+ //endfunction
+
+ // pretty sure this isn't necessary anymore, but keeping this for now since its easier
+ function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func);
+ equal = adr === adrExpected;
+ endfunction
+
+
+ `define ERROR \
+ #10; \
+ $display("processed %0d instructions with %0d warnings", instrs, warningCount); \
+ $stop;
+
+ logic [63:0] pcExpected;
+ logic [63:0] regExpected;
+ integer regNumExpected;
+ logic [`XLEN-1:0] PCW;
+
+ flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
+
+ genvar i;
+ generate
+ for(i=1; i<32; i++) begin
+ always @(dut.hart.ieu.dp.regf.rf[i]) begin
+ if ($time == 0) begin
+ scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
+ if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin
+ $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
+ `ERROR
+ end
+ end else begin
+ scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
+ scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
+ if (i != regNumExpected) begin
+ $display("%0t ps, instr %0d: wrong register changed: %0d, %0d expected to switch to %x from %x", $time, instrs, i, regNumExpected, regExpected, dut.hart.ieu.dp.regf.rf[regNumExpected]);
+ `ERROR
+ end
+ if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin
+ $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
+ `ERROR
+ end
+ //if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
+ // force dut.hart.ieu.dp.regf.rf[i] = regExpected;
+ // release dut.hart.ieu.dp.regf.rf[i];
+ //end
+ end
+ end
+ end
+ endgenerate
+
+ // RAM and bootram are addressed in 64-bit blocks - this logic handles R/W
+ // including subwords. Brief explanation on signals:
+ //
+ // readMask: bitmask of bits to read / write, left-shifted to align with
+ // nearest 64-bit boundary - examples
+ // HSIZE = 0 -> readMask = 11111111
+ // HSIZE = 1 -> readMask = 1111111111111111
+ //
+ // In the linux boot, the processor spends the first ~5 instructions in
+ // bootram, before jr jumps to main RAM
+
+ logic [63:0] readMask;
+ assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0];
+
+ logic [`XLEN-1:0] readAdrExpected, readAdrTranslated;
+
+ always @(dut.HRDATA) begin
+ #2;
+ if (dut.hart.MemRWM[1]
+ && (dut.hart.ebu.CaptureDataM)
+ && dut.HRDATA !== {64{1'bx}}) begin
+ //$display("%0t", $time);
+ if($feof(data_file_memR)) begin
+ $display("no more memR data to read");
+ `ERROR
+ end
+ scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
+ scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
+ assign readAdrTranslated = adrTranslator(readAdrExpected);
+ if (~equal(HADDR,readAdrTranslated,4)) begin
+ $display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrTranslated);
+ `ERROR
+ end
+ if ((readMask & HRDATA) !== (readMask & dut.HRDATA)) begin
+ if (HADDR inside `LINUX_FIX_READ) begin
+ //$display("warning %0t ps, instr %0d, adr %0d: forcing HRDATA to expected: %x, %x", $time, instrs, HADDR, HRDATA, dut.HRDATA);
+ force dut.uncore.HRDATA = HRDATA;
+ #9;
+ release dut.uncore.HRDATA;
+ warningCount += 1;
+ end else begin
+ $display("%0t ps, instr %0d: ExpectedHRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE);
+ `ERROR
+ end
+ end
+ //end else if(dut.hart.MemRWM[1]) begin
+ // $display("%x, %x, %x, %t", HADDR, dut.PCF, dut.HRDATA, $time);
+
+ end
+
+ end
+
+ logic [`XLEN-1:0] writeDataExpected, writeAdrExpected, writeAdrTranslated;
+
+ // this might need to change
+ //always @(HWDATA or HADDR or HSIZE or HWRITE) begin
+ always @(negedge HWRITE) begin
+ //#1;
+ if ($time != 0) begin
+ if($feof(data_file_memW)) begin
+ $display("no more memW data to read");
+ `ERROR
+ end
+ scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
+ scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
+ assign writeAdrTranslated = adrTranslator(writeAdrExpected);
+
+ if (writeDataExpected != HWDATA && ~dut.uncore.HSELPLICD) begin
+ $display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
+ `ERROR
+ end
+ if (~equal(writeAdrTranslated,HADDR,1) && ~dut.uncore.HSELPLICD) begin
+ $display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrTranslated);
+ `ERROR
+ end
+ end
+ end
+
+ integer totalCSR = 0;
+ logic [99:0] StartCSRexpected[63:0];
+ string StartCSRname[99:0];
+ initial begin
+ while(1) begin
+ scan_file_csr = $fscanf(data_file_csr, "%s\n", StartCSRname[totalCSR]);
+ if(StartCSRname[totalCSR] == "---") begin
+ break;
+ end
+ scan_file_csr = $fscanf(data_file_csr, "%x\n", StartCSRexpected[totalCSR]);
+ totalCSR = totalCSR + 1;
+ end
+ end
+
+ always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin
+ if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 2 && instrs > 1) begin
+ $display("!!!!!! illegal instruction !!!!!!!!!!");
+ $display("(as a reminder, MCAUSE and MEPC are set by this)");
+ $display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR);
+ `ERROR
+ end
+ if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin
+ $display("!!!!!! illegal (physical) memory access !!!!!!!!!!");
+ $display("(as a reminder, MCAUSE and MEPC are set by this)");
+ $display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR);
+ `ERROR
+ end
+ end
+
+ `define CHECK_CSR2(CSR, PATH) \
+ string CSR; \
+ logic [63:0] expected``CSR``; \
+ //CSR checking \
+ always @(``PATH``.``CSR``_REGW) begin \
+ if ($time > 1) begin \
+ if ("SEPC" == `"CSR`") begin #1; end \
+ if ("SCAUSE" == `"CSR`") begin #2; end \
+ if ("SSTATUS" == `"CSR`") begin #3; end \
+ scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
+ scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
+ if(CSR.icompare(`"CSR`")) begin \
+ $display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \
+ end \
+ if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
+ $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
+ `ERROR \
+ end \
+ end else begin \
+ if (!(`BUILDROOT == 1 && "MSTATUS" == `"CSR`")) begin \
+ for(integer j=0; j<totalCSR; j++) begin \
+ if(!StartCSRname[j].icompare(`"CSR`")) begin \
+ if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
+ $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
+ `ERROR \
+ end \
+ end \
+ end \
+ end \
+ end \
+ end
+ `define CHECK_CSR(CSR) \
+ `CHECK_CSR2(CSR, dut.hart.priv.csr)
+ `define CSRM dut.hart.priv.csr.genblk1.csrm
+ `define CSRS dut.hart.priv.csr.genblk1.csrs.genblk1
+
+
+ //`CHECK_CSR(FCSR)
+ `CHECK_CSR2(MCAUSE, `CSRM)
+ `CHECK_CSR(MCOUNTEREN)
+ `CHECK_CSR(MEDELEG)
+ `CHECK_CSR(MEPC)
+ //`CHECK_CSR(MHARTID)
+ `CHECK_CSR(MIDELEG)
+ `CHECK_CSR(MIE)
+ //`CHECK_CSR(MIP)
+ `CHECK_CSR2(MISA, `CSRM)
+ `CHECK_CSR2(MSCRATCH, `CSRM)
+ `CHECK_CSR(MSTATUS)
+ `CHECK_CSR2(MTVAL, `CSRM)
+ `CHECK_CSR(MTVEC)
+ //`CHECK_CSR2(PMPADDR0, `CSRM)
+ //`CHECK_CSR2(PMdut.PCFG0, `CSRM)
+ `CHECK_CSR(SATP)
+ `CHECK_CSR2(SCAUSE, `CSRS)
+ `CHECK_CSR(SCOUNTEREN)
+ `CHECK_CSR(SEPC)
+ `CHECK_CSR(SIE)
+ `CHECK_CSR2(SSCRATCH, `CSRS)
+ `CHECK_CSR(SSTATUS)
+ `CHECK_CSR2(STVAL, `CSRS)
+ `CHECK_CSR(STVEC)
+
+ logic speculative;
+ initial begin
+ speculative = 0;
+ end
+ logic [63:0] lastCheckInstrD, lastPC, lastPC2;
+
+ string PCtextW, PCtext2W;
+ logic [31:0] InstrWExpected;
+ logic [63:0] PCWExpected;
+ always @(PCW or dut.hart.ieu.InstrValidW) begin
+ if(dut.hart.ieu.InstrValidW && PCW != 0) begin
+ if($feof(data_file_PCW)) begin
+ $display("no more PC data to read");
+ `ERROR
+ end
+ scan_file_PCW = $fscanf(data_file_PCW, "%s\n", PCtextW);
+ PCtext2W = "";
+ while (PCtext2W != "***") begin
+ PCtextW = {PCtextW, " ", PCtext2W};
+ scan_file_PC = $fscanf(data_file_PCW, "%s\n", PCtext2W);
+ end
+ scan_file_PCW = $fscanf(data_file_PCW, "%x\n", InstrWExpected);
+ // then expected PC value
+ scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
+ if(~equal(PCW,PCWExpected,2)) begin
+ $display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, PCW, PCWExpected);
+ `ERROR
+ end
+ //if(it.InstrW != InstrWExpected) begin
+ // $display("%0t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
+ //end
+ end
+ end
+
+ string PCtext, PCtext2;
+ initial begin
+ instrs = 0;
+ end
+ logic [31:0] InstrMask;
+ logic forcedInstr;
+ logic [63:0] lastPCD;
+ always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin
+ if(~HWRITE) begin
+ #2;
+ if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin
+ if (dut.hart.ifu.PCD !== lastPCD) begin
+ lastCheckInstrD = CheckInstrD;
+ lastPC <= dut.hart.ifu.PCD;
+ lastPC2 <= lastPC;
+ if (speculative && (lastPC != pcExpected)) begin
+ speculative = ~equal(dut.hart.ifu.PCD,pcExpected,3);
+ if(dut.hart.ifu.PCD===pcExpected) begin
+ if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs
+ (dut.hart.ifu.PCD == 32'h80001dc6) || // as well as stores to PLIC
+ (dut.hart.ifu.PCD == 32'h80001de0) ||
+ (dut.hart.ifu.PCD == 32'h80001de2)) begin
+ $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
+ force CheckInstrD = 32'b0010011;
+ force dut.hart.ifu.InstrRawD = 32'b0010011;
+ while (clk != 0) #1;
+ while (clk != 1) #1;
+ release dut.hart.ifu.InstrRawD;
+ release CheckInstrD;
+ warningCount += 1;
+ forcedInstr = 1;
+ end
+ else begin
+ forcedInstr = 0;
+ end
+ end
+ end
+ else begin
+ if($feof(data_file_PC)) begin
+ $display("no more PC data to read");
+ `ERROR
+ end
+ scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
+ PCtext2 = "";
+ while (PCtext2 != "***") begin
+ PCtext = {PCtext, " ", PCtext2};
+ scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
+ end
+ scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD);
+ if(dut.hart.ifu.PCD === pcExpected) begin
+ if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs
+ (dut.hart.ifu.PCD == 32'h80001dc6) || // as well as stores to PLIC
+ (dut.hart.ifu.PCD == 32'h80001de0) ||
+ (dut.hart.ifu.PCD == 32'h80001de2)) begin
+ $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
+ force CheckInstrD = 32'b0010011;
+ force dut.hart.ifu.InstrRawD = 32'b0010011;
+ while (clk != 0) #1;
+ while (clk != 1) #1;
+ release dut.hart.ifu.InstrRawD;
+ release CheckInstrD;
+ warningCount += 1;
+ forcedInstr = 1;
+ end
+ else begin
+ forcedInstr = 0;
+ end
+ end
+ // then expected PC value
+ scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
+ if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
+ (instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
+ (instrs <= 100000 && instrs % 10000 == 0) || (instrs <= 1000000 && instrs % 100000 == 0)) begin
+ $display("loaded %0d instructions", instrs);
+ end
+ instrs += 1;
+ // are we at a branch/jump?
+ if (`BPRED_ENABLED) begin
+ speculative = dut.hart.ifu.bpred.bpred.BPPredWrongE;
+ end else begin
+ casex (lastCheckInstrD[31:0])
+ 32'b00000000001000000000000001110011, // URET
+ 32'b00010000001000000000000001110011, // SRET
+ 32'b00110000001000000000000001110011, // MRET
+ 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
+ 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
+ 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
+ 32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
+ 32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
+ 32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
+ speculative = 1;
+ 32'bXXXXXXXXXXXXXXXX1001000000000010, // C.EBREAK:
+ 32'bXXXXXXXXXXXXXXXXX000XXXXX1110011: // Something that's not CSRR*
+ speculative = 0; // tbh don't really know what should happen here
+ 32'b000110000000XXXXXXXXXXXXX1110011, // CSR* SATP, *
+ 32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
+ 32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
+ speculative = 1;
+ default:
+ speculative = 0;
+ endcase
+ end
+
+ //check things!
+ if ((~speculative) && (~equal(dut.hart.ifu.PCD,pcExpected,3))) begin
+ $display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, dut.hart.ifu.PCD, pcExpected);
+ `ERROR
+ end
+ InstrMask = CheckInstrD[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
+ if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.InstrRawD) !== (InstrMask & CheckInstrD))) begin
+ $display("%0t ps, instr %0d: InstrD does not equal CheckInstrD: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.InstrRawD, CheckInstrD, dut.hart.ifu.PCD);
+ `ERROR
+ end
+ end
+ end
+ lastPCD = dut.hart.ifu.PCD;
+ end
+ end
+ end
+
+ // Track names of instructions
+ string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+ logic [31:0] InstrW;
+ instrTrackerTB it(clk, reset,
+ dut.hart.ifu.icache.controller.FinalInstrRawF,
+ dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
+ dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
+ InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+ // generate clock to sequence tests
+ always
+ begin
+ clk <= 1; # 5; clk <= 0; # 5;
+ end
+
+endmodule
+module instrTrackerTB(
+ input logic clk, reset,
+ input logic [31:0] InstrF,InstrD,InstrE,InstrM,InstrW,
+ output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+ // stage Instr to Writeback for visualization
+ //flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
+
+ instrNameDecTB fdec(InstrF, InstrFName);
+ instrNameDecTB ddec(InstrD, InstrDName);
+ instrNameDecTB edec(InstrE, InstrEName);
+ instrNameDecTB mdec(InstrM, InstrMName);
+ instrNameDecTB wdec(InstrW, InstrWName);
+endmodule
+
+// decode the instruction name, to help the test bench
+module instrNameDecTB(
+ input logic [31:0] instr,
+ output string name);
+
+ logic [6:0] op;
+ logic [2:0] funct3;
+ logic [6:0] funct7;
+ logic [11:0] imm;
+
+ assign op = instr[6:0];
+ assign funct3 = instr[14:12];
+ assign funct7 = instr[31:25];
+ assign imm = instr[31:20];
+
+ // it would be nice to add the operands to the name
+ // create another variable called decoded
+
+ always_comb
+ casez({op, funct3})
+ 10'b0000000_000: name = "BAD";
+ 10'b0000011_000: name = "LB";
+ 10'b0000011_001: name = "LH";
+ 10'b0000011_010: name = "LW";
+ 10'b0000011_011: name = "LD";
+ 10'b0000011_100: name = "LBU";
+ 10'b0000011_101: name = "LHU";
+ 10'b0000011_110: name = "LWU";
+ 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
+ else name = "ADDI";
+ 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
+ else name = "ILLEGAL";
+ 10'b0010011_010: name = "SLTI";
+ 10'b0010011_011: name = "SLTIU";
+ 10'b0010011_100: name = "XORI";
+ 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
+ else if (funct7[6:1] == 6'b010000) name = "SRAI";
+ else name = "ILLEGAL";
+ 10'b0010011_110: name = "ORI";
+ 10'b0010011_111: name = "ANDI";
+ 10'b0010111_???: name = "AUIPC";
+ 10'b0100011_000: name = "SB";
+ 10'b0100011_001: name = "SH";
+ 10'b0100011_010: name = "SW";
+ 10'b0100011_011: name = "SD";
+ 10'b0011011_000: name = "ADDIW";
+ 10'b0011011_001: name = "SLLIW";
+ 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
+ else if (funct7 == 7'b0100000) name = "SRAIW";
+ else name = "ILLEGAL";
+ 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
+ else if (funct7 == 7'b0100000) name = "SUBW";
+ else name = "ILLEGAL";
+ 10'b0111011_001: name = "SLLW";
+ 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
+ else if (funct7 == 7'b0100000) name = "SRAW";
+ else name = "ILLEGAL";
+ 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
+ else if (funct7 == 7'b0000001) name = "MUL";
+ else if (funct7 == 7'b0100000) name = "SUB";
+ else name = "ILLEGAL";
+ 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
+ else if (funct7 == 7'b0000001) name = "MULH";
+ else name = "ILLEGAL";
+ 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
+ else if (funct7 == 7'b0000001) name = "MULHSU";
+ else name = "ILLEGAL";
+ 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
+ else if (funct7 == 7'b0000001) name = "DIV";
+ else name = "ILLEGAL";
+ 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
+ else if (funct7 == 7'b0000001) name = "MUL";
+ else name = "ILLEGAL";
+ 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
+ else if (funct7 == 7'b0000001) name = "DIVU";
+ else if (funct7 == 7'b0100000) name = "SRA";
+ else name = "ILLEGAL";
+ 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
+ else if (funct7 == 7'b0000001) name = "REM";
+ else name = "ILLEGAL";
+ 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
+ else if (funct7 == 7'b0000001) name = "REMU";
+ else name = "ILLEGAL";
+ 10'b0110111_???: name = "LUI";
+ 10'b1100011_000: name = "BEQ";
+ 10'b1100011_001: name = "BNE";
+ 10'b1100011_100: name = "BLT";
+ 10'b1100011_101: name = "BGE";
+ 10'b1100011_110: name = "BLTU";
+ 10'b1100011_111: name = "BGEU";
+ 10'b1100111_000: name = "JALR";
+ 10'b1101111_???: name = "JAL";
+ 10'b1110011_000: if (imm == 0) name = "ECALL";
+ else if (imm == 1) name = "EBREAK";
+ else if (imm == 2) name = "URET";
+ else if (imm == 258) name = "SRET";
+ else if (imm == 770) name = "MRET";
+ else name = "ILLEGAL";
+ 10'b1110011_001: name = "CSRRW";
+ 10'b1110011_010: name = "CSRRS";
+ 10'b1110011_011: name = "CSRRC";
+ 10'b1110011_101: name = "CSRRWI";
+ 10'b1110011_110: name = "CSRRSI";
+ 10'b1110011_111: name = "CSRRCI";
+ 10'b0001111_???: name = "FENCE";
+ default: name = "ILLEGAL";
+ endcase
+endmodule
+